Clock is initialized at 1 instead of 0

[johnsbrew]

Having main clock initialized at 1instead of 0 will hide underlying issues at t=0. We discovered this issue while interconnecting some chisel code using synchronous reset with existing SV blackboxes using Preset and we add hard time troubleshooting the issue at t=0.

Delaying first posedge clock (and hence associated synchronous reset operation) enabled us to understand rather easily what was really going on.

I set it as default for the VSIMBackend

[chick]

Is this a problem with Treadle (I'm guessing no given the black boxes etc). Treadle does have the ability to set the phase offset off the clock through command line or annotation, and it's default phase offset is 1.

Also has a PR to fix 0 not being allowed as phase shift value