David Fang comments

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                                            David Fang

Add Google's Verible verilog formatter for verilog, systemverilog files

@hzeller @msfschaffner This might be an alternative way to support formatting for your project environment.

Structure literal formatting issues

Nice test case. It is know that the wrapping implementation needs a lot of work. @ldalek-antmicro FYI

Feature request: support `pre-commit` hook

Can you specify what you have in mind for pre-commit? the style-lint-clean? format-clean? both? See also: https://github.com/google/verible/blob/master/verilog/tools/formatter/git-verilog_format.sh This runs the formatter on the current workspace, and formats _changed lines_ only....

Feature request: support `pre-commit` hook

@eunchan @imphil @msfschaffner -- might be interested

Backslash before newline in comment triggers indentation

I am fairly certain this is the fault of the "InterLeaf" state machine that sweeps up non-syntax tokens in the Verilog tree_unwrapper.cc. A recent change in the lexer separated out...

Token partition tree check failure (fuzzer finding)

FYI: b/259099842 for this issue was just automatically closed as not-reproducible

Resolve "Rejected valid signal name"

The `verilog.output` file is a "human-readable" state machine of the parser, which explains how conflicting states are reached.

nested replication construct rejected syntax

b/176992014

Parsing error in formatter

Yikes, it looks like it dropped the function's input parameters in the problematic output!

Assign alignment breaks when line length would go over column limit

Acknowledged and confirmed, the alignment logic is conservative at the moment, it that it won't expand past the column limit. Extending this behavior remains to be specified: how to handle...