Unnecessary top padding with V_TOP node labels and inside port label

[uruuru]

Consider the graph below. It looks as if the label placement code reserves space for a potential inside north port label even though there is no such label. Note that changing the south port to a north port does in fact use the available space.

With portLabels.placement: INSIDE:

Without (I would deem this expected behavior):

algorithm: layered

node n2 {
    layout [ size: 100, 100]
    portConstraints: FIXED_SIDE
    nodeLabels.placement: "INSIDE V_TOP H_CENTER"
    portLabels.placement: INSIDE

    port pw {
        ^port.side: WEST
    }
    port pe {
        ^port.side: EAST
    }
    port ps {

        ^port.side: SOUTH
        label "south"
    }

    label "text" {
        layout [ size: 20, 10 ]
    }
    label "text2" {
        layout [ size: 40, 10 ]
    }
}

[soerendomroes]

This seems to be a feature. If one sets nodeSize.options: ASYMMETRICAL it should be fixed. The following snippet in StripContainerCell produces the issue:

// If we are to be symmetrical, the outer cells need to be the same size
if (symmetrical) {
  cellHeights[0] = Math.max(cellHeights[0], cellHeights[2]);
  cellHeights[2] = cellHeights[0];
}

Here cellHeights[0] is everything above the cell and cellHeight[2] everything below.

I think however, that this is not a good solution since it also seems to move ports.