PCBFlow

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no SUBCKT if loading from verilog instead of GHDL

7

I slightly modified one of the provided flows to replace the GHDL step with: ``` read_verilog -sv -formal ../main.sv ../vinclude/*.sv hierarchy -check -top Mover proc ``` but the generated spice...

nonchip

PCB Placement: Could not insert I/O cell in line zero

9

Hi, I tried to use PCBFlow on a VHDL design of mine. In particular, it is a complex adder(my implementation of the Pentium 4 Adder). After some trial and error...

mkexc

``` # TODO: Keep track of merged net assignment to allows merging multiple connected nets ``` https://github.com/cpldcpu/PCBFlow/blob/881925be87ee0536a80e3b9b6c9fd37e241011a7/30_PLACE/PCBPlace.py#L780

cpldcpu

https://github.com/cpldcpu/PCBFlow/blob/21e2a06220da6948100eabec706c5362df03297a/30_PLACE/PCBPlace.py#L256

cpldcpu

--- For more details, open the [Copilot Workspace session](https://copilot-workspace.githubnext.com/cpldcpu/PCBFlow/pull/8?shareId=bf0eecf3-de49-43af-abce-fc5656567897).

cpldcpu

Refactor the `30_PLACE/PCBPlace.py` file to improve readability and maintainability. * **Constants**: Add constants for default values such as `DEFAULT_PITCH_X`, `DEFAULT_PITCH_Y`, `DEFAULT_ARRAY_X_WIDTH`, etc. * **Code Cleanup**: Remove commented-out code and unnecessary...

cpldcpu