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                                            Uiop Pilon

thor: I/O APIC IRQs don't start off masked

I thought limine left all IRQs masked, since afaik, it's in the stivale spec. Were you using multiboot by any chance?

thor: I/O APIC IRQs don't start off masked

Ahh, that explains it then

thor: Implement AMD SVM

I could tackle this one, as for I have SVM support in my os

How To Run On A Real PC

@thecoder08 I tried balena etcher but it didn’t work. As for the recommendation to use dd, I don’t know how to do that and wish you would further explain how...

How To Run On A Real PC

Thanks for the help