[docs] Update file export description

[towoe]

Use emitSystemVerilogFile and emitCHIRRTLFile to export the corresponding files. Fix runMain command. Files are saved as SystemVerilog '.sv'. Do not use (use circt.stage.ChiselStage) as this appears not to work anymore.

Contributor Checklist

• [ ] Did you add Scaladoc to every public function/method?
• [ ] Did you add at least one test demonstrating the PR?
• [ ] Did you delete any extraneous printlns/debugging code?
• [ ] Did you specify the type of improvement?
• [ ] Did you add appropriate documentation in docs/src?
• [x] Did you request a desired merge strategy?
• [ ] Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Documentation or website-related

Desired Merge Strategy

• Squash: The PR will be squashed and merged (choose this if you have no preference).

Release Notes

Reviewer Checklist (only modified by reviewer)

• [ ] Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• [ ] Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
• [ ] Did you review?
• [ ] Did you check whether all relevant Contributor checkboxes have been checked?
• [ ] Did you do one of the following when ready to merge:
  • [ ] Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
  • [ ] Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

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[towoe]

Hi, I was just playing around with Chisel and tried to get some SV and FIRRTL out. Came across the description and seemed not to work for me. From the code I gathered that there have been some updates which might not be reflected in the docs. But maybe it was just me not being able to get to run as in the FAQs mentioned.

[towoe]

Thanks for the comment @jackkoenig. I also had the feeling that this could use some more improvements, but just wanted to start where I had some touch points.

I am with Hochschule München now, which should be a member of Chips Alliance, so I marked @wallento to approve this.