chisel
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a problem about DonCare
I have new a module as follow,
val mod = Module(fuGen(null, 0))
mod.io <> DontCare
mod io was set dontcare and output is not needed, in theory, mod should be removed in transalated verilog.
but it appears in verilog. How can i remove in finnal rtl, (my purpose is to use some function in mod)