Reflective naming will override the name given by naming plugin

[jackkoenig]

Consider

class Example extends Module {
  val foo, bar = IO(Input(UInt(8.W)))
  val out      = IO(Output(UInt(8.W)))
  
  val sum = foo + bar
  dontTouch(sum)
  
  // Reflection here overwrites the name of sum
  val fuzz = sum

  out := sum
}

If you generate Verilog from this, you will get the following:

module Example(
  input        clock,
  input        reset,
  input  [7:0] foo,
  input  [7:0] bar,
  output [7:0] out
);
  wire [7:0] fuzz = foo + bar; // @[main.scala 10:17]
  assign out = fuzz; // @[main.scala 15:7]
endmodule

Scastie: https://scastie.scala-lang.org/RMgRfAfKTpmtAgKOxBxnZQ

Note that this only occurs because fuzz is earlier in the alphabet than sum and the reflective naming is done in alphabetical order.

I plan to fix this in 3.6 by removing all reflective naming. We could attempt to fix this as a bug fix in a minor version, but because the required change is so intrusive and breaks some [bad & deprecated] APIs, I think it's simplest just to change this on the major version.

Type of issue: bug report

Impact: API modification | unknown

Development Phase: request

Other information

If the current behavior is a bug, please provide the steps to reproduce the problem:

What is the current behavior?

See above

What is the expected behavior?

See above

Please tell us about your environment:

What is the use case for changing the behavior?

More predictable naming behavior

[jackkoenig]

Incidentally, this problem is super unpredictable. It seems that merely adding some extra vals can make the issue go away...

class Example extends Module {
  val foo, bar = IO(Input(UInt(8.W)))
  val out      = IO(Output(UInt(8.W)))

  val x = 3.U

  val sum = foo + bar + x
  dontTouch(sum)

  val a = x
  // For some reason sum is no longer renamed
  val fuzz = sum + a

  out := sum
}

module Example(
  input        clock,
  input        reset,
  input  [7:0] foo,
  input  [7:0] bar,
  output [7:0] out
);
  wire [7:0] _sum_T_1 = foo + bar; // @[main.scala 11:17]
  wire [7:0] sum = _sum_T_1 + 8'h3; // @[main.scala 11:23]
  assign out = sum; // @[main.scala 18:7]
endmodule

Scastie: https://scastie.scala-lang.org/w2est82CTrGZn3tWlqUI0g