sub field assignment

[schoeberl]

As I cannot reopen issue #878, I created a new one. If this is too hard to implement then we can close it again (maybe with an argument).

Subword (individual bit) assignment should be possible in Chisel (like in V*).

I have students stumbled over this several times.

It is a very common pattern in Verilog and VHDL to consider a multi-bit wire or signal just as an indexable collection of bits. Many textbook examples in VHDL and Verilog are written in this style, e.g., the Dally book uses this extensively.

By adding another standard example to my book (simple arbiter), I stumbled again self over this issue. Here is a code example.

  val grant = WireDefault(0.U(3.W))

  grant(0) := request(0)
  notGranted(0) := ~grant(0)
  grant(1) := request(1) & notGranted(0)
  notGranted(1) := ~grant(1) & notGranted(0)
  grant(2) := request(2) & notGranted(1)

Those are all UInts. I know that I can work around with VecInit(io.request.asBools) and grant.asUInt.

[ekiwi]

I was working on a firrtl pass for "de-sugaring" sub-word assignments at the beginning of this year: https://github.com/ekiwi/firrtl/tree/sub-word-assign Unfortunately it turned out to be more than just a weekend project. It is probably more like 3-4 full-time engineering weeks.