chipsalliance
logic_net includes [net_drivers] and [net_loads]
Currently I did not get any data from [net_drivers] and [net loads]. have any future plan of it?
Not at this time. Surelog does not create a fully connected flattened netlist (which is needed to make that computation). I can imagine an incremental procedure that build that data on demand based on the UHDM model and modify the UHDM model (R/W) for the logic cone in the query. It would have to perform bit-blasting on demand and connect the bits/vector splices. This is probably best done in the UHDM code base itself as a utility (Not in Surelog).
I have no bandwidth to work on this, but I'll help anyone who wants to take a stabb at it.