capstone-engine
Plan for future development of Capstone
This is a rough plan to continue Capstone development after v4.0. Exact timeline is to be updated.
~~### Version 4.1~~
~~This version is now developed in https://github.com/aquynh/capstone/tree/v4.1.~~
~~Features:~~ ~~- Include some bugfixes for version 4.0~~ ~~- Update for SystemZ~~ ~~- New architecture MOS65XX~~
Update: since this breaks bindings (see #1315), we bumped the major version to v5.
Version 5.0
This version is developed in https://github.com/aquynh/capstone/tree/next.
This is a major update for all architectures, and will hopefully add few more from LLVM 7.0.x.
- Sync with latest code from LLVM, focusing on X86, Arm, Arm64, Mips, PowerPC & Sparc. This would bring in latest instruction sets for all these architectures.
- Better toolset to generate instruction meta data from LLVM tablegen, to make it easier to sync with future update of LLVM. Currently this is painful, requiring adhoc manual work.
- New architectures to be considered to support: MSP430, ARC, AVR & RISCV. (RiscV already had a pull req https://github.com/aquynh/capstone/pull/1198)
- We may also add WebAsm architecture
Bindings
Except Python, most existing bindings become broken when we upgraded from v3.0.5 to v4.0. See https://github.com/aquynh/capstone/issues/1315 for more details.
Binding authors should at least update their cs_insn structure, so their bindings can work. Beyond that, we hope they continue to support all the new features introduced in v4.0.
~~Update: we merged the branch v4.1 to the master branch. The next release will be v4.1~~
Update: since branch master breaks bindings, i marked its version as 5.0 instead.
We still have some maintenance versions for v4.0.x. The next release will be v4.0.2, where we just cherry-pick bugfixes. Track this version in branch ~~https://github.com/aquynh/capstone/tree/v4.0.2~~ https://github.com/aquynh/capstone/tree/v4
some quick updates on development on the "next" branch.
- i synced X86 with LLVM 7.0.1, and now we support latest X86 extensions.
- we have regression test under suite/cstest now. all the closed issues should be put into https://github.com/aquynh/capstone/blob/next/suite/cstest/issues.cs, which is verified on every commit with Travis. thanks to this, we will not regress on fixed issues.
now X86 is done, i am moving to ARM. expect update soon.
for the "next" branch (will be released as v5.0), we got few more new architectures in MOS65xx, BPF, WASM & RISCV. more will come in the near future, before 5.0 is out.
We just had a huge update on ARM, so now we can handle can latest instructions from v8.1a ~ v8.4a specs.
Check it out in the "next" branch at https://github.com/aquynh/capstone/tree/next
Next update will be Aarch64.
AArch64 architecture is updated, and should support all the latest instructions now.
Check it out in the "next" branch at https://github.com/aquynh/capstone/tree/next
I am now moving to update PowerPC.
woah :DDD thank you! i can confirm it works as expected for the PAC instructions at least, will update r2 git and see if there's any regression
On 10 Apr 2019, at 12:02, Nguyen Anh Quynh [email protected] wrote:
AArch64 architecture is updated, and should support all the latest instructions now.
Check it out in the "next" branch at https://github.com/aquynh/capstone/tree/next https://github.com/aquynh/capstone/tree/next I am now moving to update PowerPC.
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PowerPC is updated, see https://github.com/aquynh/capstone/tree/next.
The remaining important architectures to be updated are Mips & Sparc.
@aquynh can you create an organization? So multiple people can manage the repository? Or @radareorg can adopt the project, thanks.
Newer ARMv8 instructions are needed to be updated again: https://github.com/aquynh/capstone/issues/1650
Would it be possible to update the instruction set for existing ARCHs like AArch64 on the current version and PyPI package? I'm using this in my project DyldExtractor, but it seems to stop disassembling on recent PAC instructions like RETAB and PACIBSP.
