fejkon
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Fibre Channel / FICON HBA implemented on FPGA
After a big break and mentally going over things that need to be debugged and issues I'm having, mostly related to PCIe, I have decided to put this project to...
Apparently the System Console allows for making dashboards and widgets. That would be really cool to give a board overview like ID, PCIe stats, and SFP data. See https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_system_console.pdf page...
Alex has also moved to cocotb recently so we should move to his library instead of our own pcie.py when time permits: https://github.com/alexforencich/cocotbext-pcie
- [ ] Create a fejkon.sof.git with the revision hash in it - [ ] Make syscon load fejkon.sof on startup - [ ] Warn if the detected board is...
Right now the signal integrity on the SFP channels has not been a issue, and likely will not be. However I have been playing around with the Eye viewer and...
From the LowRISC style guide it is apparent that they are using asynchronous reset and active-low. Thinking about it, that does make a whole lot of sense, and might mean...
From #63 research. We are using synchronized resets, so we should make sure the system is adequately set up to generate those. In essence this likely means changing some "deassert"...
From playing around with fejkon with some actual FC traffic it has become clear that there will be a need to capture behavior on the primitives. For example when debugging...
This might be a useful feature to surface state information to user space.
I don't recall why I chose LF2 as the default state, it seems LF1 would be a more logical choice to avoid having to go LF2 -> LF1 as the...