Björn Quentin
Björn Quentin
Thanks for reporting this! I am a bit confused since the toolchain you added says `targets = [ "riscv32imac-unknown-none-elf" ]` but your command-line says `target/riscv32imc-unknown-none-elf/debug/examples/timer_interrupt` ... but it's quite early...
Thanks for the update! The problem with opt-level "z" is really interesting. I'm a bit surprised to see those problems with the RV32 targets but something like that can happen...
Thanks for the detailed analysis! Good job! The reason why `get_status` uses u128 is that on the Xtensa based chips we indeed need more than 64 bits and we want...
Thanks for the update! I'd personally vote for the second option especially since this problem might also get triggered in user-code.
I guess this is resolved now - reopen if you don't agree
Parts of that upper memory is also used by ROM functions etc. AFAIK. Plus (not really applies here since it's direct-boot) the 2nd stage bootloader uses some memory there that...
Thanks a lot for your contribution! The only thing I am not sure about: Maybe we want higher-level examples like this go into (the still empty) https://github.com/esp-rs/esp-hal-examples repository as a...
Sounds good to me
Awesome progress! Thanks for working on this I personally don't have experience with TAWI/CAN so I hope that someone else can participate. (@jessebraham @MabezDev ?) Maybe one nit-pick alrready would...
Going to implement first steps to get I2S support (starting with ESP32-C3 / ESP32-S3 - then ESP32 and ESP32-S2, just TX for the start and only supporting standard I2S -...