Rework compiler backend with register allocation and SSA-based mid-level IR.

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The current compiler backend goes directly from an abstract syntax tree to a list of instructions. It'd be easier to perform analyses and implement new compiler optimizations on an SSA form, that gets lowered to the instruction list we currently have. In particular, this addition should help us implement register allocation, which should significantly improve language performance.

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AsmJit might be of help here.

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Added to 1.0 release in the new "releases" project. Work is progressing on this in compiler/ssa.cpp! Register allocation has largely been moved to the new Jasmine bytecode instruction set.