microwatt
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antonblanchard
A tiny Open POWER ISA softcore written in VHDL 2008
This series reduces the number of metavalue warnings; all the console tests now have 47 warnings, and the last warning is at 25ns. Somehow this also reduces LUT utilization by...
I'd like to graph the usage of FPGA resource usage over time so we can easily see when things bloat. When building microwatt.json, you get a report from yosys like...
Add a test case so that we don't introduce latches into the build. These can be found by building microwatt.json and yosys will output: ` Warning: found logic loop in...
Add a test case so that we don't introduce warning into the build again. #390 fixed a bunch of these recently, but it would be nice to make sure they...
This adds valentyusb as a uart, works for orangecrab though should be applicable to other platforms. I'm leaving this as a draft pull request because the software side needs a...
Commits 07f2edc / 780d6c7 port microwatt across an incompatible API change in litedram. Unfortunately, newer litedram no longer works on Genesys2 (and possibly on NexysVideo and Nexys4DDR, as @fontamsoc reports...
Creative commons is not meant for licensing software. https://creativecommons.org/faq/#can-i-apply-a-creative-commons-license-to-software It is even in doubt if it is an open source license, since it is not listed here: https://opensource.org/licenses/alphabetical https://www.gnu.org/licenses/license-list.html
After getting GHDL to emit some more information about metavalue assertions, the worst offenders are (the first column is the number of times I saw the assertion): ``` 3431 in...
Hi! I am new to this project and am trying to build it for the first time, I am facing the following issue: ``` ghdl -c --std=08 -Psim-unisim -Wl,sim_vhpi_c.o -Wl,sim_bram_helpers_c.o...
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A tiny Open POWER ISA softcore written in VHDL 2008