Trying to change read interface to AXI4, getting elaboration errors when generating verilog

[seandextercrevinn]

Steps to recreate:

1. Have dependencies installed (sbt, jdk, scala), clone fastvdma repo, and navigate to the cloned repo directory.

2. Make the following edits:

File: src/main/scala/DMAController/DMATop.scala Line 36:

-    val read = Flipped(new AXIStream(DMATop.readDataWidth))
+    val read = Flipped(new AXI4(DMATop.addrWidth, DMATop.readDataWidth))

Line 44

-  val readerFrontend = Module(new AXIStreamSlave(DMATop.addrWidth, DMATop.readDataWidth))
+  val readerFrontend = Module(new AXI4Reader(DMATop.addrWidth, DMATop.readDataWidth))

3. Run "make verilog"

I get the following elaboration error: [error] (run-main-0) chisel3.internal.ChiselException: Connection between left (DMAController.Bus.AXI4@203) and source (DMAController.Bus.AXI4@42b) failed @.r.rready: Both Left and Right are drivers

Is there something I'm missing? Perhaps some documentation is needed to guide through the steps to modify the bus protocol for each of the three interfaces (Ctrl, ReadData & WriteData)? Let me know what you think.

[seandextercrevinn]

Changing Line 36 instead to:

-    val read = Flipped(new AXIStream(DMATop.readDataWidth))
+    val read = new AXI4(DMATop.addrWidth, DMATop.readDataWidth)

... seems to have allowed it to compile. Please advise whether this is correct.

[piotr-binkowski]

Hi @seandextercrevinn

This change is the correct way to use AXI4 (with Flipped removed)

As for documentation, I think a short guide on modifying bus protocols used would be useful.