vex

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TODO: - [ ] Fully understand what I just changed. - [ ] Add a test case.

ltfish

Per the docs, PC used in ADR should have a +4 added

1

See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473c/Cacdbfji.html I am a bit concerned there are other places missing this.

subwire

API Calls representation in VEX

9

### Question Hi, I need some guidance regarding VEX IR for API calls of ELF files for MIPS/ARM binaries. I have seen VEX IR for different assembly instructions however unable...

nav60

s390 EXLR will probably segfault if target is outside the current segment

1

see #20 and #19 The correct solution is to do an IR-based implementation of s390_irgen_EXRL.

rhelmot

Spechelper for FP compares

1

I am trying to get a symbolic expression from an ARM64 code performing floating point compares. The function takes single `float` argument in reg `s0` which I have initialized as...

udiboy1209

shaymargolis

### Description On x86-32, this decodes to: ``` 0: d4 00 aam 0x0 ``` On x86-64 this should be an invalid instruction byte sequence, however pyvex will decode it properly....

mborgerson

riscv64: shift instructions can behave wrong

5

### Description The RISCV64 ISA specifications say that the shift operations: - sra, srl, sll use the lowest 6 bits of rd2 - sraw, srlw, sllw use the lowest 5...

Cskorpion

read from zero register in RISCV should always return 0

1

### Description Currently, `GET:I64(zero)` will not be resolved to 0, instead, it will read the symbolic value in the register ### Steps to reproduce the bug _No response_ ### Environment...

Kyle-Kyle