openfpga-litex

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Add video.json scaler_slot to APF_BRIDGE [WIP]

2

Files with non-derived changes: `docs/control.md`, `litex/verilog_platform.py`, `litex/csr.py`, `target/pocket/core_top.sv` How I built this: ``` (cd litex && PATH=$PATH:/home/mcc/work/r/v/usr/bin make) (cd lang/rust/crates/litex-pac/ && make) (cd projects && ~/usr/intelFPGA_lite/22.1std/quartus/bin/quartus_sh --flow compile openFPGA-RISC-V_pocket) (export...

mcclure

This started occurring to me when building Rust projects. After some tracking down, this is specifically caused due to some `slint` change that took place in `1.5.0`. https://github.com/slint-ui/slint/issues/4046

agg23

How can I tell when a deferred file read is finished?

14

I'm all up and running with the core and having fun putting together a little Slint app, but I've hit a roadblock with the deferred file loading API. This might...

kcsmnt0

There is (seemingly 100% consistent) vertical tearing when VBLANK deadline is met

1

Theoretically, the idea with openfpga-litex optimization is that you start writing to the framebuffer when video status (`peripherals.APF_VIDEO.video.read()`) `.vblank_triggered().bit()` goes high, and you finish before video status `.vblank_status().bit()` goes low....

mcclure

## Overview This PR implements proper synchronization for cartridge pins and interface signals to prevent metastability issues when crossing clock domains. It adds a parameterized two-stage synchronizer module and introduces...

eric-humane