Alex Williams

> FYI, the questionable primitive got added in #13152 and was discussed / reviewed by people with visibility into the closed source side. I'll bring this up in a meeting...

These all seem to be passing now--I fixed up several of these along the way. We're not at 100% at this point, though: - i2c_csr_bit_bash overflows FIFOs and triggers assertions...

> Thx for reporting this issue @jwnrt. Adding to M4 to ensure we resolve this in time. > > > This test (which runs in `rma`, `dev`, and `test_unlocked1`) has...

> The test has started passing again with some recent RTL changes today, but it doesn't look like it was intentionally fixed. This could mean the issue still exists but...

It might help if I could understand the desired feature set and where topgen currently falls short. For this case of "multiple CPUs within the OpenTitan complex," what sort of...

> Right now, I envision multiple CPUs that have their own maps but share common infrastructure from the RoT CPU. For example, the RoT Ibex has one alert manager connected...

This doesn't matter so much for the `earlgrey_es_sival` branch, but if you've been using a given bazel workspace across commits on a branch with active hardware development, note that you'll...

Notice `execvp()` fails because it can't find the updatemem binary. It's not on your PATH. Make sure you source the settings64.sh script in the installation directory to set the required...

Hm... that's peculiar. I haven't used that particular version before... I wonder if there is an incorrectly-placed license check or something. Also, FYI, if you are not developing FPGA designs...

Did you actually enable the cache in software? The Verilog parameter affects whether the cache is present in hardware. The default state of the CPU still leaves the cache inactive....