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ATSAME51J20A chip

Open r4gus opened this issue 3 years ago • 0 comments

  • MAIN_CLK
    • 48MHz on startup via DFLL48M -> GCLK0 -> GCLK_MAIN
  • GPIO
    • PA{0..31}
    • PB{0..31}
  • UART
    • Via SERCOM5 (PB16 (TX) and PB17 (RX))
    • Clocked by GCLK2 at 48MHz

r4gus avatar Sep 10 '22 23:09 r4gus