Xilinx
Can the XUP vitis network design work with 10G/25G Ethernet IP instead of the existing 100GEthernet IP ?
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Usign Vitis 2021.2 or older? Make sure the Y2K22 patch is applied
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Does this design support 10G Ethernet IP targeted on Alveo u50?
- I observe that the output from the 100G Ethernet IP CMAC kernel is 512 bit AXI4 stream whereas for 10G Ethernet the output is 64 bit.
- The CDC logic to convert from kernel clock to the 100G Ethernet subsystem clock can also support for 10G ethernet subsystem?
- The No. of lanes for 100G Ethernet is {4x25}, can this be modified to support for 10G ethernet?
- Is the 100G ethernet subsystem register mapping compatible for 10G Ethernet IP? These are some of the differences I observe between the 100G and 10G Ethernet subsystem, are there more differences which I need to make note of for further implementation or changes?
Hi @lizajoseph,
This repository and associated IP will only work for 100 G. There is no current plan to support any other speed. There is a substantial body of work to support 10G. I suggest you check the 10/25G Ethernet IP, the modifications to this project are not trivial.
The CMAC kernel as it is designed here will not work for 10G.
