RTL ConvInpGen: Dynamic FM dimensions

[fpjentzsch]

Summary

Exposes control registers to enable re-programming of the RTL SWG during runtime. The RTL component is generated once for the largest required configuration in terms of buffer depth (e.g., the largest FM dimensions) and can then adapt to arbitrary changes in FM dimension (stride and dilation also possible) as long as they fit inside the buffer. Kernel, bitwidth, and folding configuration remain constant.

This "dynamic" mode will co-exist with the normal implementation via a node attribute switch ("dynamic_mode").

Interface

Currently implements an AXI-Lite register file that holds 16 configuration parameters, which are generated from within the SWG HLSCustomOp. The AXI registers are attached to input signals of the core component in a wrapper, so it would be straightforward to attach a different interface (e.g., stream-based).

To make use of existing FINN infrastructure for rtlsim (such as hook functions before simulation starts), the unit test (test_fpgadataflow_slidingwindow_rtl_dynamic) uses stitched-ip-rtlsim, similar to the Checksum layer. This test also shows how the programming procedure works:

1. Write all 15 configuration parameters to the AXI-Lite register file
2. Assert the cfg_valid input (also controlled via an AXI-Lite register) for at least 1 clock cycle
3. Reset the component (ap_rst_n) for at least 1 clock cycle. Also resets all AXI registers to 0 (including the cfg_valid flag)

Note: The component's internal registers are initialized to the original FM dimension. However, it is still recommended to perform this procedure (including reset of the complete accelerator pipeline) before every use.

Depends on / includes

• [x] https://github.com/Xilinx/finn/pull/607

ToDo

• [ ] Simulation/HW test in realistic conv-layer context (Yaman)
• [ ] Cleanup