Xilinx
Optional performance monitoring hooks into rtlsim loop
Currently we extract data from .vcd traces for performance debugging purposes. This can get very slow for large networks as the traces can be huge, and the cycle-by-cycle behavior has to be reconstructed.
An alternative to this is to add a monitoring hook inside the rtlsim loop that would log the desired statistics cycle-by-cycle. This may decrease the emulation performance somewhat, but is still likely to be faster as it would avoid the disk I/O associated with writing/reading traces.
The prerequisite for getting this done is fixing the internal signal view support in PyVerilator -- at the moment the sim.internal_signals is not populated (empty) for FINN rtlsim. This seems to be due to some name-based filtering PyVerilator is doing.
