Xilinx
XSpiPs Reset value causes first transfer to be handled differently than subsequent transfers
https://github.com/Xilinx/embeddedsw/blob/be4f96f3f73b0e47036eeb77949c1cc638b7648c/XilinxProcessorIPLib/drivers/spips/src/xspips_hw.h#L97
After many hours of diagnosing the problem, we found that the XSpi driver for SPI interfaces sets the reset state of the driver to NOT have any Chip Select active.
The XSpiPs driver, however, has a reset value that sets Chip Select to 0 upon cfgInitialize. This causes the first transaction on the SPI line's to have zero delay between the clock becoming active and the chip select being asserted.
After a transaction is completed, the reset state becomes "no chip selected" and subsequent transfers have an appropriate delay between the clock and chip select lines.
This is primarily seen in manual chip select mode.
In auto chip select mode, the driver also has issues between transfers where the chip select line is de-asserted for a fraction of the clock cycle, and can cause problems with SPI devices that communicate with 16-bit transfers as they perceive the chip select bump as a deassertion.
@jwolfm98 thanks for pointing it out.
Agree with you, we had made required driver changes and will push for next release, once testing is done.
@jwolfm98 Manual chip select mode: Reset value of SPI Controller Configuration register CS[13:10] bit field is zero, with XSpiPs_Enable call in transfer result in no delay between zero delay between the clock becoming active and the chip select being asserted Updated XSpiPs_Reset function to address this issue by de-asserting the chip selection by default, with this change first and subsequent transaction will be the same.
Current logic: https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/spips/src/xspips.c#L234
Updated logic: XSpiPs_WriteReg(InstancePtr->Config.BaseAddress, XSPIPS_CR_OFFSET, XSPIPS_CR_RESET_STATE | XSPIPS_CR_SSCTRL_MASK );
Auto chip select mode: SPI controller have FIFO width 8-bit, for 16-bit data transfer two entries required, if there any delay writing in second FIFO entry leads to FIFO empty status controller can de-asserting the chip selection line, hence for this use case we may need to use Manual chip select mode instead of Auto chip select mode.
Please let me if you have any questions.
