TTC init code does not clear interrupts

[dnotq]

In this code:

https://github.com/Xilinx/embeddedsw/blob/be4f96f3f73b0e47036eeb77949c1cc638b7648c/XilinxProcessorIPLib/drivers/ttcps/src/xttcps.c#L239

The call to clear the TTC interrupt register (offset 0x54) should be a register READ, not a write. The register is clear-on-read, and the write is ignored. Tested on MPSoC K26 RPU.

How it is now, the initialization code for the timer does not reset any previous interrupts that were not cleared for whatever reason (software crash, core forced to quit, etc.)

Also, the pair of macros XTtcPs_GetInterruptStatus and XTtcPs_ClearInterruptStatus are very misleading. They both do the exact same register read, however the names suggest that getting and clearing the timer ISR can be done in two steps.

There should be one macro with a more appropriate name like XTtcPs_ReadAndClearInterruptStatus, or some such thing.

Matthew

[sivadur]

@dnotq Thanks for reporting. We will look into it and fix as needed.