Xilfpga: Fix PL reset sequence when programming FPGA

[RussellJoyce]

This patch brings the EMIO PL resets low before the PL power is enabled when programming the FPGA, and raises them again afterwards. This prevents the PL logic from running briefly in the period between programming and triggering the reset signals.

The current reset sequence causes problems, as the FPGA design (including any MicroBlaze code) will run for a few thousand cycles before the reset signal is triggered after programming.

[NavaKishoreManne]

Hi RussellJoyce,

Thanks for providing the fix...

The logic looks good to me but this a critical fix as it's related to resets. so we need to test all our existing test cases with this fix. if everything goes cool will push this changes into the next release

unfortunately we won't merge pull request to this repo. So for the next time onwards Please send the patches to [email protected] alias using git send-email command. If you are not sure how to do that steps are provided here http://www.wiki.xilinx.com/Create+and+Submit+a+Patch

Regards, Navakishore.