Xilinx
freertos_intr_example.c example does not work on R5 core on ZCU104 - no interrupts are delievered
Please re-test the example found here: https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/examples/freertos_intr_example.c. It doesn't work, and I'm not the first to notice: https://forum.digilent.com/topic/24684-zynq-ultrascale-example-with-freertos-using-interrupts-on-a-uart-or-other-interrupt-source/
All my TTCs are enabled in Vivado. The baremetal example (https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/ttcps/examples/xttcps_intr_example.c) does work, suggesting there is a problem with how the GIC and FreeRTOS are integrated.
I am using Vivado and Vitis 2022.2.
Thanks for pointing out on this. Let me try it here and get back.
regards, Anirudha
Based on my observations, I see that if xiltimer is disabled and I try it, it works. I am checking why with xiltimer enabled, it might fail.
Based on my observations, I see that if xiltimer is disabled and I try it, it works. I am checking why with xiltimer enabled, it might fail.
Here's a possible cause I hit on another project: When xiltimer is enabled, the port uses xiltimer to provide the FreeRTOS tick interrupt. But if xiltimer's en_interval_timer is left as 'false' (which is the default), the interval timer is never configured and it seems no ticks are ever generated. I think there needs to be a sanity check so if that if FreeRTOS is in use, and xiltimer is enabled, then en_interval_timer must be enabled.
See here: https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/bsp/freertos10_xilinx/src/Source/portable/GCC/ARM_CR5/portZynqUltrascale.c#L144
Edited previous comment to clarify. I think the problem is with 'en_interval_timer', not 'interval_timer'.
We have raised a bug request and it will be fixed in the next 2023.2 release. We will also post information abt the patch in this forum/discussion thread to get your review comments.