What's the rationale behind writing PCI_STATUS_INTERRUPT(0x8) to the PCI_STATUS register?

[Jiaqigege]

Dear developers: I am working on the XDMA with A7. I try to compare the PCIe Spec and xdma kernel code. I came across a piece of code that I didn't understand. The code writes PCI_STATUS_INTERRUPT(0x8) to the PCI_STATUS configuration space register. Upon consulting the specification, I found that bit 3 of this register is read-only, while the other bits are write-1-to-clear. I'm curious as to why this action was taken, what was the reasoning behind it?

dma_ip_drivers/XDMA/linux-kernel/xdma/libxdma.c: line 1873-1883

static void pci_check_intr_pend(struct pci_dev *pdev)
{
	u16 v;

	pci_read_config_word(pdev, PCI_STATUS, &v);
	if (v & PCI_STATUS_INTERRUPT) {
		pr_info("%s PCI STATUS Interrupt pending 0x%x.\n",
			dev_name(&pdev->dev), v);
		pci_write_config_word(pdev, PCI_STATUS, PCI_STATUS_INTERRUPT);
	}
}