XRT
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Xilinx
Run Time for AIE and FPGA based platforms
Adding clock throttling feature support on versal platforms. Added all required changes in tools, user space driver, and in xgq driver. This PR enables user to check the clock throttling(scaling)...
Hw Context is in place. This PR is targeted to enable hw context changes for PCIe shim, XOCL driver, KDS core. This changes are align with XRT core hw context...
#### Problem solved by the commit The following new values were suggested for AIE_trace_settings.start_type configuration [AIE_trace_settings] start_type = time|iteration|kernel_event0 "time" will be the default. #### Risks (if any) associated the...
#### Problem solved by the commit realloc() returns a NULL if reallocation was not successful. This was not handled properly (by returning `new_size` after conditional execution `free(temp)`. More info on...
#### Problem solved by the commit https://jira.xilinx.com/browse/VITIS-5838 The Versal platform introduces the idea of PS kernels, which are a type of software application that runs onboard a device's APU. The...
#### Problem solved by the commit Enable XGQ interrupt from ERT to host. #### Risks (if any) associated the changes in the commit Low #### What has been tested and...
#### Problem solved by the commit Move PS kernel return code after arguments in the command buffer #### Bug / issue (if any) fixed, which PR introduced the bug, how...
Introduce a new data structure i.e. islot_info from icap. XCLBIN related information is separated from icap structure and added to the new islot_info data structure. This is required for multislot...
Updated latest petalinux version to XRT/build/petalinux.build
#### Problem solved by the commit in new platform, vdu drivers would be in blacklist at boot time. These modules should be loaded once dynamic region is loaded. As there...
