Xilinx
PYNQ support for AXI4lite and/or AXI4 output ports in a block design
Pynq version: 3.0.1 Board: zcu104
The particular port can be controlled either via zynq processing part or jtag programmer, if I program the bitstream, I am able to access the register set using this port via jtag programmer. But if I use pynq to program it, it is throwing an error (KeyError: ‘axi4lite_m0’).
Can you be more specific as to what function you are calling and how you are calling it?
Or can you provide the full stack trace when the error is thrown?
Can you be more specific as to what function you are calling and how you are calling it?
Or can you provide the full stack trace when the error is thrown?
Hi, I am not calling any particular function, I am just trying to program the device using the overlay object and it throws this error.
Stack Trace: File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/overlay.py:319, in Overlay.init(self, bitfile_name, dtbo, download, ignore_version, device, gen_cache) 315 super().init(bitfile_name, dtbo, partial=False, device=device) 317 self._register_drivers() → 319 self.device.set_bitfile_name(self.bitfile_name) 320 self.parser = self.device.parser 322 self.ip_dict = ( 323 self.gpio_dict 324 ) = ( 325 self.interrupt_controllers 326 ) = self.interrupt_pins = self.hierarchy_dict = dict()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/device.py:118, in Device.set_bitfile_name(self, bitfile_name) 116 def set_bitfile_name(self, bitfile_name: str) → None: 117 self.bitfile_name = bitfile_name → 118 self.parser = self.get_bitfile_metadata(self.bitfile_name) 119 self.mem_dict = self.parser.mem_dict 120 self.ip_dict = self.parser.ip_dict
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:690, in EmbeddedDevice.get_bitfile_metadata(self, bitfile_name, partial) 689 def get_bitfile_metadata(self, bitfile_name:str, partial:bool=False): → 690 parser = _get_bitstream_handler(bitfile_name).get_parser(partial=partial) 691 if parser is None: 692 raise RuntimeError(“Unable to find metadata for bitstream”)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynq/pl_server/embedded_device.py:254, in BitstreamHandler.get_parser(self, partial) 252 parser = self._get_cache() 253 except CacheMetadataError: → 254 parser = RuntimeMetadataParser(Metadata(input=self._filepath.with_suffix(“.hwh”))) 255 except: 256 raise RuntimeError(f"Unable to parse metadata")
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/metadata.py:40, in Metadata(input) 38 if os.path.isfile(input): 39 if str(input).endswith(“.hwh”): —> 40 return HwhFrontend(_hwhfile=input) 41 elif str(input).endswith(“.xsa”): 42 return XsaFrontend(input=input)
File :25, in init(self, name, type, generic_type, _parent, _children, ref, ext, _timestamp, hierarchy_name, ports, parameters, blocks, modules, busses, _hierarchies, _hwhfile, _element_tree, _root, _logical2physical_portmap, _physical2logical_portmap, _logical2physical_extern_pm, _physical2logical_extern_pm)
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:219, in HwhFrontend.post_init(self) 207 “”" 208 Performs the parsing of the hwh into the metadata model 209 * checks to see if the hwhfile is an XML string or a (…) 216 * Performs a connectivity pass 217 “”" 218 if self._hwhfile != “”: → 219 self.parse()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:240, in HwhFrontend.parse(self) 237 self._construct_logical2physical_extern_pm() 238 self._create_external_ports() → 240 self.resolve_addressing() 241 self.connect_signals() 243 self.refresh()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:596, in HwhFrontend.resolve_addressing(self) 589 def resolve_addressing(self) → None: 590 “”" 591 For all the subordinate ports in the design and manager ports 592 grab all the addressing information 593 WARNING: This should only be called after all the cores and ports 594 have been populated. 595 “”" → 596 self._resolve_subordinate_addressing() 597 self._populate_subordinate_regmap() 598 self._resolve_manager_address_maps()
File /usr/local/share/pynq-venv/lib/python3.10/site-packages/pynqmetadata/frontends/hwh_frontend.py:452, in HwhFrontend._resolve_subordinate_addressing(self) 450 for i in self._root.iter(“MEMRANGE”): 451 if i.get(“MEMTYPE”) == “REGISTER” or i.get(“MEMTYPE”) == “MEMORY”: → 452 core = self.blocks[i.get(“INSTANCE”)] 453 port = core.ports[i.get(“SLAVEBUSINTERFACE”)] 454 if isinstance(port, SubordinatePort):
KeyError: ‘axi4lite_m0’