Risc-V and mips support ?

[eix128]

is there any support for risc-v and mips in future ?

[Wunkolo]

Not really... I don't have a MIPS or Risc-V machine to research code on but I am very open to PRs!

[eix128]

hmm , what about Qemu VM to test ?

[Wunkolo]

I suppose so. MIPS has a flag that can be enabled in user-space that causes all load/store instructions to use a reverse byte endian, so a pattern I would imagine for a MIPS64 implementation of qReverse would be

Reverse64:
        dsbh    $2,$4
        dshd    $2,$2

which is how __builtin_bswap64 is implemented. So, in theory building qReverse on a gcc compiler targetting MIPS64 would already see speedups. So that work is implicitly already done.

RISC-V doesn't exactly lend itself to a fast in-register byte reverse though I don't think. I've never worked with either and can't think of an instruction that would lend itself for a qReverse acceleration.