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verified publisher icon Velocidex

pre-emption and landing on another cpu processor during read/write action causes corruption

Open vivianezw opened this issue 2 years ago • 1 comments

A interrupt disable/enable sequence (or anything preventing us from getting pre-empted and moved to another cpu processor) is needed for a secure read/write. Already verified empirically. To do on next occasion. Without the fix, anybody might end up reading/writing to false location, so beware.

vivianezw avatar Jan 22 '24 07:01 vivianezw

Fixed, but requires testing first. So this stays open until then.

Please remember this is an alpha version and please do report any potential bugs!

vivianezw avatar May 11 '24 13:05 vivianezw

Confirmed to work.

vivianezw avatar Jun 04 '24 18:06 vivianezw