VLSIDA
LVS mismatch errors in SKY130 SRAM
I am encountering LVS mismatch issues while generating a single-port SRAM using the Sky130 technology. Could the problem be related to num_spare_col and num_spare_row in our config? How can I address and resolve this issue?
Another issue I'm facing is that the spare_wen pin is not in the lib file. Also, the power values in the lib file appear to be excessively large, around 10^9. Can you provide guidance on how to address this?
My OpenRAM version is v1.2.45. |==============================================================================| |========= OpenRAM v1.2.42 =========| |========= =========| |========= VLSI Design and Automation Lab =========| |========= Computer Science and Engineering Department =========| |========= University of California Santa Cruz =========| |========= =========| |========= Usage help: [email protected] =========| |========= Development help: [email protected] =========| |========= See LICENSE for license info =========| |==============================================================================| ** Start: 12/18/2023 02:25:16 Technology: sky130 Total size: 128 bits Word size: 8 Words: 16 Banks: 1 RW ports: 1 R-only ports: 0 W-only ports: 0 DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking). Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate). Only generating nominal corner timing. Words per row: None Output files are: /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.lvs /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.sp /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.v /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.lib /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.py /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.html /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.log /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.lef /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.gds ** Submodules: 2.9 seconds ** Placement: 0.0 seconds ** Routing: 158.3 seconds ERROR: file magic.py: line 385: sram_1rw_8_16_sky130 LVS mismatch (results in /tmp/openram_root_24133_temp/sram_1rw_8_16_sky130.lvs.report)
** Verification: 169.8 seconds ** SRAM creation: 331.1 seconds SP: Writing to /home/user/OpenRAM/result/sram_1rw_8_16_sky130/sram_1rw_8_16_sky130.sp ** Spice writing: 0.1 seconds
