Feature request: port groups

[amb5l]

My application needs an object hierarchy to represent VHDL design units and their contents. I want to capture port grouping information - where sets of port clauses have empty lines and/or comments between them - so I have created a fork of pyVHDLModel with support for port groups. It is backward compatible with the standard (flat) way of accessing port information.

Would it make any sense to make a PR to allow port groups to be considered here?