Zero register destination operands in multi-destination register AArch64 instructions

[jj16791]

In #352, an update was made to address the issue with zero registers as destination operands. Namely, the results vector has been modified to include entries for these zero registers in its tail elements whilst the destinationRegisters vector has zero registers excluded. I.e.

results = {{implicit destinations}, {explicit non-zero registers}, {explicit zero registers}}

destinationRegisters = {{implicit destinations}, {explicit non-zero registers}}

This way, zero registers destination indexes can be consumed in the instruction execution logic but not written to at the writeback stage or equivalent.

An issue arises when there's a mismatch between results and destinationRegisters indexes. For example, take an instruction with the destination registers of xzr and x0. The results vector would therefore have two entries with xzr = results[0] and x0 = results[1]. In our writeback stage, we iterate over the results vector and set the corresponding register (the same vector index) in destinationRegisters to be that value. In this case, destinationRegisters[0] == x0 and thus x0 = results[0] not results[1] like it should. You also run into the issue of trying to access destinationRegisters[1] which doesn't exist.