OpenROAD
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The-OpenROAD-Project
Add actionable error message when PDN doesn't fit between core and die area
Describe the bug
The detailed routing spends ca. 20 minutes to get through 0 and 1st iteration, then things proceed pretty quickly and it gets stuck(infinite loop?) in the 51st iteration.
To reproduce:
- untar https://drive.google.com/file/d/19y3gw2DL9BOteXvEMB07GBcrMngT5fvp/view?usp=sharing
- run below
$ NUM_CORES=16 ./run-me-FpPipeline-asap7-base.sh
OpenROAD v2.0-11602-g18cbc8d2b
[deleted]
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 72941 violations.
elapsed time = 00:01:43, memory = 23246.29 (MB).
Completing 20% with 56039 violations.
elapsed time = 00:03:00, memory = 23356.55 (MB).
Completing 30% with 49203 violations.
elapsed time = 00:03:48, memory = 23667.76 (MB).
Completing 40% with 37493 violations.
elapsed time = 00:05:51, memory = 24035.68 (MB).
Completing 50% with 32494 violations.
elapsed time = 00:06:17, memory = 22973.07 (MB).
Completing 60% with 32494 violations.
elapsed time = 00:07:57, memory = 23971.48 (MB).
Completing 70% with 19858 violations.
elapsed time = 00:09:16, memory = 23713.82 (MB).
Completing 80% with 15360 violations.
elapsed time = 00:10:07, memory = 24022.12 (MB).
Completing 90% with 6137 violations.
elapsed time = 00:12:09, memory = 24350.66 (MB).
Completing 100% with 3126 violations.
elapsed time = 00:12:31, memory = 23257.75 (MB).
[INFO DRT-0199] Number of violations = 3592.
Viol/Layer M1 M2 M3 V3 M4 V4 M5 V5
CutSpcTbl 0 0 0 55 0 11 0 2
EOL 0 388 8 0 2 0 0 0
Metal Spacing 80 76 234 0 5 0 70 0
Recheck 6 259 183 0 18 0 0 0
Short 8 204 3 0 3 0 23 0
eolKeepOut 0 1902 38 0 11 0 3 0
[INFO DRT-0267] cpu time = 03:08:15, elapsed time = 00:12:35, memory = 22662.84 (MB), peak = 24556.07 (MB)
Total wire length = 1041540 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 296351 um.
Total wire length on LAYER M3 = 401157 um.
Total wire length on LAYER M4 = 197543 um.
Total wire length on LAYER M5 = 101650 um.
Total wire length on LAYER M6 = 30231 um.
Total wire length on LAYER M7 = 12775 um.
Total wire length on LAYER M8 = 1829 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1450472.
Up-via summary (total 1450472):.
------------------
Active 0
M1 469522
M2 841059
M3 114855
M4 20500
M5 3458
M6 941
M7 137
M8 0
M9 0
------------------
1450472
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 3592 violations.
elapsed time = 00:00:33, memory = 23634.98 (MB).
Completing 20% with 3178 violations.
elapsed time = 00:00:49, memory = 23311.73 (MB).
Completing 30% with 3072 violations.
elapsed time = 00:01:04, memory = 23409.81 (MB).
Completing 40% with 2731 violations.
elapsed time = 00:01:41, memory = 23313.86 (MB).
Completing 50% with 2667 violations.
elapsed time = 00:01:44, memory = 22406.85 (MB).
Completing 60% with 2667 violations.
elapsed time = 00:02:20, memory = 23354.41 (MB).
Completing 70% with 2296 violations.
elapsed time = 00:02:35, memory = 23064.76 (MB).
Completing 80% with 2244 violations.
elapsed time = 00:02:50, memory = 23353.98 (MB).
Completing 90% with 1896 violations.
elapsed time = 00:03:25, memory = 23494.27 (MB).
Completing 100% with 1829 violations.
elapsed time = 00:03:29, memory = 22406.82 (MB).
[INFO DRT-0199] Number of violations = 2055.
Viol/Layer M1 M2 V2 M3 V3 M4 V4 M5
CutSpcTbl 0 0 0 0 11 0 4 0
EOL 0 239 0 5 0 0 0 0
Metal Spacing 45 46 0 111 0 0 0 70
Recheck 4 147 0 101 0 9 0 0
Short 1 106 1 3 0 1 0 23
eolKeepOut 0 1107 0 18 0 3 0 0
[INFO DRT-0267] cpu time = 00:51:43, elapsed time = 00:03:32, memory = 22087.69 (MB), peak = 24556.07 (MB)
[deleted]
[INFO DRT-0195] Start 50th optimization iteration.
Completing 10% with 75 violations.
elapsed time = 00:00:00, memory = 21224.53 (MB).
Completing 20% with 51 violations.
elapsed time = 00:00:08, memory = 21224.53 (MB).
Completing 30% with 37 violations.
elapsed time = 00:00:15, memory = 21224.53 (MB).
Completing 40% with 37 violations.
elapsed time = 00:00:15, memory = 21224.53 (MB).
Completing 50% with 37 violations.
elapsed time = 00:00:15, memory = 21224.53 (MB).
Completing 60% with 37 violations.
elapsed time = 00:00:15, memory = 21224.53 (MB).
Completing 70% with 34 violations.
elapsed time = 00:00:21, memory = 21224.53 (MB).
Completing 80% with 24 violations.
elapsed time = 00:00:24, memory = 21224.53 (MB).
Completing 90% with 24 violations.
elapsed time = 00:00:24, memory = 21224.53 (MB).
Completing 100% with 24 violations.
elapsed time = 00:00:24, memory = 21224.53 (MB).
[INFO DRT-0199] Number of violations = 24.
Viol/Layer M5
Metal Spacing 19
Short 5
[INFO DRT-0267] cpu time = 00:00:40, elapsed time = 00:00:24, memory = 21224.53 (MB), peak = 24556.07 (MB)
[deleted]
[INFO DRT-0195] Start 51st optimization iteration.
Completing 10% with 24 violations.
elapsed time = 00:00:00, memory = 21224.53 (MB).
[no further output]
DRC snapshot above is for the .rpt file of the 50th iteration.
Expected Behavior
Complete in a reasonable amount of time
Environment
OpenROAD v2.0-11602-g18cbc8d2b
To Reproduce
See above
Relevant log output
No response
Screenshots
No response
Additional Context
No response
Did you observe a similar slow down in iter 44? We periodically try a more aggressive rip up strategy.
Something is wrong as you have pdn stripes going outside the core area. Please investigate earlier in the flow what is going wrong.
@osamahammad21 if we have drc between a pin shape and a fixed shape we should fail early.
@osamahammad21 if we have drc between a pin shape and a fixed shape we should fail early.
Does that mean we need to check_drc before routing and check for such drcs?
That's a bit challenging as we normally skip possible violations among fixed shapes. And when we do route, we merge the pin shape with the net segment connecting to it under one gcNet (to have correct max rectangles and polygon edges).
Something is wrong as you have pdn stripes going outside the core area. Please investigate earlier in the flow what is going wrong.
@maliberty To reproduce the problem of power strips being generated outside of the die area:
- untar https://drive.google.com/file/d/1GKoMeZo_xHGD9DcGK5C1skHCowcvZgrc/view?usp=sharing
- Run
./run-me-FpPipeline-asap7-base.sh - Zoom in on top edge
I would be nice to stop a doomed run early. I don't want to spend a lot of time looking for a rare case though. If you see an easy/fast way to detect it then please do so otherwise c'est la vie.
I would be nice to stop a doomed run early. I don't want to spend a lot of time looking for a rare case though. If you see an easy/fast way to detect it then please do so otherwise c'est la vie.
I can't recall detailed routing running into an infinite loop in this way, I'd be wary of adding conditional code for such a rare case... You'd definitely need automated test cases for such rare conditions or it will bit rot anyway.
@maliberty So the root cause is PDN, for which I created a reproduction case in https://github.com/The-OpenROAD-Project/OpenROAD/issues/4466#issuecomment-1873351593 ?
Did you observe a similar slow down in iter 44? We periodically try a more aggressive rip up strategy.
Yes, I suppose... See bottom.
Lots of warnings at the top...
$ ./run-me-FpPipeline-asap7-base.sh
OpenROAD v2.0-11602-g18cbc8d2b
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[WARNING STA-0357] virtual clock clock_vir can not be propagated.
Error: detail_route.tcl, 11 can't read "::env(NUM_CORES)": no such variable
openroad>
oyvind@corona:~/megaboom/foo$ NUM_CORES=16 ./run-me-FpPipeline-asap7-base.sh
OpenROAD v2.0-11602-g18cbc8d2b
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[WARNING STA-0357] virtual clock clock_vir can not be propagated.
[INFO ORD-0030] Using 16 thread(s).
detailed_route -output_drc bazel-bin//reports/asap7/FpPipeline/base/5_route_drc.rpt -output_maze bazel-bin//results/asap7/FpPipeline/base/maze.log -bottom_routing_layer M2 -top_routing_layer M9 -save_guide_updates -verbose 1 -drc_report_iter_step 5
[INFO DRT-0149] Reading tech and libs.
[WARNING DRT-0140] SpacingRange unsupported.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0145] New SPACINGTABLE PARALLELRUNLENGTH overrides old SPACING rule.
[WARNING DRT-0323] Via(s) in pin VDD of regfile_128x65 will be ignored
[WARNING DRT-0323] Via(s) in pin VSS of regfile_128x65 will be ignored
Units: 1000
Number of layers: 21
Number of macros: 213
Number of vias: 11
Number of viarulegen: 11
[INFO DRT-0150] Reading design.
Error: duplicated via definition for via5_6_120_288_1_2_58_322
Design: FpPipeline
Die area: ( 0 0 ) ( 349606 349606 )
Number of track patterns: 32
Number of DEF vias: 0
Number of components: 611538
Number of terminals: 1141
Number of snets: 2
Number of nets: 159000
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_mispredict_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_brupdate_b1_resolve_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_fu_code[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_fu_code[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_bits_fu_code[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_0_ready
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_fu_code[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_fu_code[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_fu_code[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_bits_uses_stq
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_1_ready
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_fu_code[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_fu_code[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_fu_code[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_pdst[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_bits_uses_stq
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_2_ready
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_fu_code[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_fu_code[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_fu_code[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_fu_code[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_bits_uses_stq
[WARNING DRT-0422] No routing tracks pass through the center of Term io_dis_uops_3_ready
[WARNING DRT-0422] No routing tracks pass through the center of Term io_flush_pipeline
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[20]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[21]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[22]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[23]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[24]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[25]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[26]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[27]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[28]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[29]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[30]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[31]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[32]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[33]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[34]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[35]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[36]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[37]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[38]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[39]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[40]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[41]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[42]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[43]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[44]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[45]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[46]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[47]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[48]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[49]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[50]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[51]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[52]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[53]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[54]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[55]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[56]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[57]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[58]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[59]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[60]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[61]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[62]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[63]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[64]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_data[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_flags[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_flags[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_flags[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_flags[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_flags[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_fflags_valid
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_predicated
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_dst_rtype[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_dst_rtype[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_is_amo
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_pdst[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_pdst[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_pdst[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_pdst[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_pdst[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_stq_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_stq_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_stq_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_uopc[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_uopc[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_uopc[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_uopc[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_bits_uop_uses_stq
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_ready
[WARNING DRT-0422] No routing tracks pass through the center of Term io_from_int_valid
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[20]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[21]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[22]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[23]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[24]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[25]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[26]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[27]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[28]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[29]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[30]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[31]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[32]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[33]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[34]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[35]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[36]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[37]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[38]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[39]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[40]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[41]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[42]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[43]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[44]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[45]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[46]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[47]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[48]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[49]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[50]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[51]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[52]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[53]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[54]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[55]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[56]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[57]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[58]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[59]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[60]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[61]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[62]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[63]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[64]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_data[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_br_mask[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_dst_rtype[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_dst_rtype[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_is_amo
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_mem_size[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_mem_size[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_pdst[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_pdst[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_pdst[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_pdst[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_pdst[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_stq_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_stq_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_stq_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_stq_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_uopc[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_uopc[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_bits_uop_uopc[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_0_valid
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[10]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[11]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[17]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[18]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[19]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[20]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[21]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[22]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[23]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[24]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[25]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[26]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[27]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[28]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[29]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[30]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[31]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[32]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[33]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[34]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[35]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[36]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[37]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[38]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[39]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[40]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[41]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[42]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[43]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[44]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[45]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[46]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[47]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[48]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[49]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[50]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[51]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[52]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[53]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[54]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[55]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[56]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[57]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[58]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[59]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[60]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[61]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[62]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[63]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[7]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[8]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_data[9]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_mem_size[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_mem_size[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_ll_wports_1_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[27]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[34]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[35]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[36]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[38]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[40]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[44]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[47]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[48]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[51]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[54]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[57]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[58]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[59]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[60]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_data[63]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_dst_rtype[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_pdst[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_pdst[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_pdst[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_int_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[12]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[27]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[31]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[34]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[35]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[36]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[38]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[40]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[44]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[48]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[51]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[54]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[57]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[58]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[59]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[60]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_data[63]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[13]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[14]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[15]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[16]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_br_mask[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_to_sdq_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_flags[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_flags[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_flags[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_flags[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_flags[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_fflags_valid
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_predicated
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_dst_rtype[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_dst_rtype[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_0_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[5]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_1_bits_uop_rob_idx[6]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_fflags_bits_flags[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_fflags_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_fflags_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_uop_dst_rtype[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_uop_dst_rtype[1]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_uop_fp_val
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_uop_rob_idx[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_2_bits_uop_rob_idx[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_3_bits_fflags_bits_flags[0]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_3_bits_fflags_bits_flags[2]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_3_bits_fflags_bits_flags[3]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_3_bits_fflags_bits_flags[4]
[WARNING DRT-0422] No routing tracks pass through the center of Term io_wakeups_3_bits_fflags_valid
[WARNING DRT-0422] No routing tracks pass through the center of Term reset
[WARNING DRT-0240] CUT layer V3 does not have square single-cut via, cut layer width may be set incorrectly.
[WARNING DRT-0240] CUT layer V5 does not have square single-cut via, cut layer width may be set incorrectly.
[INFO DRT-0167] List of default vias:
Layer V2
default via: VIA23
Layer V3
default via: VIA34
Layer V4
default via: VIA45
Layer V5
default via: VIA56
Layer V6
default via: VIA67
Layer V7
default via: VIA78
Layer V8
default via: VIA89
Layer V9
default via: VIA9Pad
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
Complete 10000 instances.
Complete 20000 instances.
Complete 30000 instances.
Complete 40000 instances.
Complete 50000 instances.
Complete 60000 instances.
Complete 70000 instances.
Complete 80000 instances.
Complete 90000 instances.
Complete 100000 instances.
Complete 200000 instances.
Complete 300000 instances.
Complete 400000 instances.
Complete 500000 instances.
Complete 600000 instances.
[INFO DRT-0164] Number of unique instances = 412.
[INFO DRT-0168] Init region query.
[INFO DRT-0018] Complete 10000 insts.
[INFO DRT-0018] Complete 20000 insts.
[INFO DRT-0018] Complete 30000 insts.
[INFO DRT-0018] Complete 40000 insts.
[INFO DRT-0018] Complete 50000 insts.
[INFO DRT-0018] Complete 60000 insts.
[INFO DRT-0018] Complete 70000 insts.
[INFO DRT-0018] Complete 80000 insts.
[INFO DRT-0018] Complete 90000 insts.
[INFO DRT-0019] Complete 100000 insts.
[INFO DRT-0019] Complete 200000 insts.
[INFO DRT-0019] Complete 300000 insts.
[INFO DRT-0019] Complete 400000 insts.
[INFO DRT-0019] Complete 500000 insts.
[INFO DRT-0019] Complete 600000 insts.
[INFO DRT-0024] Complete Active.
[INFO DRT-0024] Complete V0.
[INFO DRT-0024] Complete M1.
[INFO DRT-0024] Complete V1.
[INFO DRT-0024] Complete M2.
[INFO DRT-0024] Complete V2.
[INFO DRT-0024] Complete M3.
[INFO DRT-0024] Complete V3.
[INFO DRT-0024] Complete M4.
[INFO DRT-0024] Complete V4.
[INFO DRT-0024] Complete M5.
[INFO DRT-0024] Complete V5.
[INFO DRT-0024] Complete M6.
[INFO DRT-0024] Complete V6.
[INFO DRT-0024] Complete M7.
[INFO DRT-0024] Complete V7.
[INFO DRT-0024] Complete M8.
[INFO DRT-0024] Complete V8.
[INFO DRT-0024] Complete M9.
[INFO DRT-0024] Complete V9.
[INFO DRT-0024] Complete Pad.
[INFO DRT-0033] Active shape region query size = 0.
[INFO DRT-0033] V0 shape region query size = 0.
[INFO DRT-0033] M1 shape region query size = 4794285.
[INFO DRT-0033] V1 shape region query size = 10580574.
[INFO DRT-0033] M2 shape region query size = 600844.
[INFO DRT-0033] V2 shape region query size = 518649.
[INFO DRT-0033] M3 shape region query size = 1046935.
[INFO DRT-0033] V3 shape region query size = 345766.
[INFO DRT-0033] M4 shape region query size = 875396.
[INFO DRT-0033] V4 shape region query size = 345766.
[INFO DRT-0033] M5 shape region query size = 370874.
[INFO DRT-0033] V5 shape region query size = 50448.
[INFO DRT-0033] M6 shape region query size = 24374.
[INFO DRT-0033] V6 shape region query size = 0.
[INFO DRT-0033] M7 shape region query size = 0.
[INFO DRT-0033] V7 shape region query size = 0.
[INFO DRT-0033] M8 shape region query size = 0.
[INFO DRT-0033] V8 shape region query size = 0.
[INFO DRT-0033] M9 shape region query size = 0.
[INFO DRT-0033] V9 shape region query size = 0.
[INFO DRT-0033] Pad shape region query size = 0.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076] Complete 100 pins.
[INFO DRT-0076] Complete 200 pins.
[INFO DRT-0076] Complete 300 pins.
[INFO DRT-0076] Complete 400 pins.
[INFO DRT-0076] Complete 500 pins.
[INFO DRT-0076] Complete 600 pins.
[INFO DRT-0076] Complete 700 pins.
[INFO DRT-0076] Complete 800 pins.
[INFO DRT-0076] Complete 900 pins.
[INFO DRT-0077] Complete 1000 pins.
[INFO DRT-0077] Complete 2000 pins.
[INFO DRT-0078] Complete 2114 pins.
[INFO DRT-0079] Complete 100 unique inst patterns.
[INFO DRT-0079] Complete 200 unique inst patterns.
[INFO DRT-0079] Complete 300 unique inst patterns.
[INFO DRT-0081] Complete 379 unique inst patterns.
[INFO DRT-0082] Complete 1000 groups.
[INFO DRT-0082] Complete 2000 groups.
[INFO DRT-0082] Complete 3000 groups.
[INFO DRT-0082] Complete 4000 groups.
[INFO DRT-0082] Complete 5000 groups.
[INFO DRT-0082] Complete 6000 groups.
[INFO DRT-0082] Complete 7000 groups.
[INFO DRT-0082] Complete 8000 groups.
[INFO DRT-0082] Complete 9000 groups.
[INFO DRT-0083] Complete 10000 groups.
[INFO DRT-0083] Complete 20000 groups.
[INFO DRT-0083] Complete 30000 groups.
[INFO DRT-0083] Complete 40000 groups.
[INFO DRT-0083] Complete 50000 groups.
[INFO DRT-0083] Complete 60000 groups.
[INFO DRT-0083] Complete 70000 groups.
[INFO DRT-0083] Complete 80000 groups.
[INFO DRT-0083] Complete 90000 groups.
[INFO DRT-0083] Complete 100000 groups.
[INFO DRT-0083] Complete 110000 groups.
[INFO DRT-0083] Complete 120000 groups.
[INFO DRT-0083] Complete 130000 groups.
[INFO DRT-0083] Complete 140000 groups.
[INFO DRT-0084] Complete 145514 groups.
#scanned instances = 611538
#unique instances = 398
#stdCellGenAp = 14390
#stdCellValidPlanarAp = 120
#stdCellValidViaAp = 11959
#stdCellPinNoAp = 0
#stdCellPinCnt = 513962
#instTermValidViaApCnt = 0
#macroGenAp = 2960
#macroValidPlanarAp = 2960
#macroValidViaAp = 0
#macroNoAp = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:01:07, elapsed time = 00:00:05, memory = 2302.05 (MB), peak = 2591.99 (MB)
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.
[INFO DRT-0156] guideIn read 500000 guides.
[INFO DRT-0156] guideIn read 600000 guides.
[INFO DRT-0156] guideIn read 700000 guides.
[INFO DRT-0156] guideIn read 800000 guides.
[INFO DRT-0156] guideIn read 900000 guides.
[INFO DRT-0157] guideIn read 1000000 guides.
Number of guides: 1462546
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 647 STEP 540 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 647 STEP 540 ;
[INFO DRT-0026] Complete 10000 origin guides.
[INFO DRT-0026] Complete 20000 origin guides.
[INFO DRT-0026] Complete 30000 origin guides.
[INFO DRT-0026] Complete 40000 origin guides.
[INFO DRT-0026] Complete 50000 origin guides.
[INFO DRT-0026] Complete 60000 origin guides.
[INFO DRT-0026] Complete 70000 origin guides.
[INFO DRT-0026] Complete 80000 origin guides.
[INFO DRT-0026] Complete 90000 origin guides.
[INFO DRT-0027] Complete 100000 origin guides.
[INFO DRT-0027] Complete 200000 origin guides.
[INFO DRT-0027] Complete 300000 origin guides.
[INFO DRT-0027] Complete 400000 origin guides.
[INFO DRT-0027] Complete 500000 origin guides.
[INFO DRT-0027] Complete 600000 origin guides.
[INFO DRT-0027] Complete 700000 origin guides.
[INFO DRT-0027] Complete 800000 origin guides.
[INFO DRT-0027] Complete 900000 origin guides.
[INFO DRT-0027] Complete 1000000 origin guides.
[INFO DRT-0027] Complete 1100000 origin guides.
[INFO DRT-0027] Complete 1200000 origin guides.
[INFO DRT-0027] Complete 1300000 origin guides.
[INFO DRT-0027] Complete 1400000 origin guides.
[INFO DRT-0028] Complete Active.
[INFO DRT-0028] Complete V0.
[INFO DRT-0028] Complete M1.
[INFO DRT-0028] Complete V1.
[INFO DRT-0028] Complete M2.
[INFO DRT-0028] Complete V2.
[INFO DRT-0028] Complete M3.
[INFO DRT-0028] Complete V3.
[INFO DRT-0028] Complete M4.
[INFO DRT-0028] Complete V4.
[INFO DRT-0028] Complete M5.
[INFO DRT-0028] Complete V5.
[INFO DRT-0028] Complete M6.
[INFO DRT-0028] Complete V6.
[INFO DRT-0028] Complete M7.
[INFO DRT-0028] Complete V7.
[INFO DRT-0028] Complete M8.
[INFO DRT-0028] Complete V8.
[INFO DRT-0028] Complete M9.
[INFO DRT-0028] Complete V9.
[INFO DRT-0028] Complete Pad.
complete 10000 nets.
complete 20000 nets.
complete 30000 nets.
complete 40000 nets.
complete 50000 nets.
complete 60000 nets.
complete 70000 nets.
complete 80000 nets.
complete 90000 nets.
complete 100000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029] Complete 10000 nets (guide).
[INFO DRT-0029] Complete 20000 nets (guide).
[INFO DRT-0029] Complete 30000 nets (guide).
[INFO DRT-0029] Complete 40000 nets (guide).
[INFO DRT-0029] Complete 50000 nets (guide).
[INFO DRT-0029] Complete 60000 nets (guide).
[INFO DRT-0029] Complete 70000 nets (guide).
[INFO DRT-0029] Complete 80000 nets (guide).
[INFO DRT-0029] Complete 90000 nets (guide).
[INFO DRT-0030] Complete 100000 nets (guide).
[INFO DRT-0035] Complete Active (guide).
[INFO DRT-0035] Complete V0 (guide).
[INFO DRT-0035] Complete M1 (guide).
[INFO DRT-0035] Complete V1 (guide).
[INFO DRT-0035] Complete M2 (guide).
[INFO DRT-0035] Complete V2 (guide).
[INFO DRT-0035] Complete M3 (guide).
[INFO DRT-0035] Complete V3 (guide).
[INFO DRT-0035] Complete M4 (guide).
[INFO DRT-0035] Complete V4 (guide).
[INFO DRT-0035] Complete M5 (guide).
[INFO DRT-0035] Complete V5 (guide).
[INFO DRT-0035] Complete M6 (guide).
[INFO DRT-0035] Complete V6 (guide).
[INFO DRT-0035] Complete M7 (guide).
[INFO DRT-0035] Complete V7 (guide).
[INFO DRT-0035] Complete M8 (guide).
[INFO DRT-0035] Complete V8 (guide).
[INFO DRT-0035] Complete M9 (guide).
[INFO DRT-0035] Complete V9 (guide).
[INFO DRT-0035] Complete Pad (guide).
[INFO DRT-0036] Active guide region query size = 0.
[INFO DRT-0036] V0 guide region query size = 0.
[INFO DRT-0036] M1 guide region query size = 437566.
[INFO DRT-0036] V1 guide region query size = 0.
[INFO DRT-0036] M2 guide region query size = 426144.
[INFO DRT-0036] V2 guide region query size = 0.
[INFO DRT-0036] M3 guide region query size = 259245.
[INFO DRT-0036] V3 guide region query size = 0.
[INFO DRT-0036] M4 guide region query size = 42556.
[INFO DRT-0036] V4 guide region query size = 0.
[INFO DRT-0036] M5 guide region query size = 10581.
[INFO DRT-0036] V5 guide region query size = 0.
[INFO DRT-0036] M6 guide region query size = 2197.
[INFO DRT-0036] V6 guide region query size = 0.
[INFO DRT-0036] M7 guide region query size = 534.
[INFO DRT-0036] V7 guide region query size = 0.
[INFO DRT-0036] M8 guide region query size = 58.
[INFO DRT-0036] V8 guide region query size = 0.
[INFO DRT-0036] M9 guide region query size = 0.
[INFO DRT-0036] V9 guide region query size = 0.
[INFO DRT-0036] Pad guide region query size = 0.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 707926 vertical wires in 13 frboxes and 470955 horizontal wires in 13 frboxes.
[INFO DRT-0186] Done with 74871 vertical wires in 13 frboxes and 96533 horizontal wires in 13 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:01:47, elapsed time = 00:00:20, memory = 6276.28 (MB), peak = 6385.58 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 6338.03 (MB), peak = 6385.58 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
Completing 10% with 0 violations.
elapsed time = 00:01:05, memory = 16720.29 (MB).
Completing 20% with 4820 violations.
elapsed time = 00:01:53, memory = 19094.59 (MB).
Completing 30% with 6805 violations.
elapsed time = 00:02:30, memory = 18924.81 (MB).
Completing 40% with 11390 violations.
elapsed time = 00:04:05, memory = 20819.16 (MB).
Completing 50% with 13149 violations.
elapsed time = 00:04:25, memory = 20084.97 (MB).
Completing 60% with 13149 violations.
elapsed time = 00:05:58, memory = 20995.05 (MB).
Completing 70% with 17584 violations.
elapsed time = 00:07:10, memory = 22517.23 (MB).
Completing 80% with 19206 violations.
elapsed time = 00:08:05, memory = 22682.21 (MB).
Completing 90% with 23518 violations.
elapsed time = 00:10:15, memory = 23993.36 (MB).
Completing 100% with 24930 violations.
elapsed time = 00:10:38, memory = 22928.15 (MB).
[INFO DRT-0199] Number of violations = 72941.
Viol/Layer M1 V1 M2 V2 M3 V3 M4 V4 M5 V5 M6 V6 M7 V7 M8
Cut Spacing 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0
CutSpcTbl 0 0 0 0 0 159 0 38 0 21 0 8 0 0 0
EOL 0 0 2240 0 62 0 26 0 0 0 0 0 0 0 0
Metal Spacing 3858 0 366 0 1705 0 24 0 70 0 3 0 0 0 10
Min Step 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11
NS Metal 142 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Recheck 26 0 29457 0 16073 0 2210 0 186 0 44 0 15 0 0
Rect Only 0 0 45 0 0 0 0 0 0 0 0 0 14 0 0
Short 831 12 1202 20 148 3 14 4 28 7 68 8 0 4 0
eolKeepOut 0 0 13440 0 208 0 123 0 0 0 0 0 0 0 0
[INFO DRT-0267] cpu time = 02:37:21, elapsed time = 00:10:41, memory = 21656.30 (MB), peak = 24241.76 (MB)
Total wire length = 1046029 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 298085 um.
Total wire length on LAYER M3 = 404114 um.
Total wire length on LAYER M4 = 197301 um.
Total wire length on LAYER M5 = 101674 um.
Total wire length on LAYER M6 = 30224 um.
Total wire length on LAYER M7 = 12784 um.
Total wire length on LAYER M8 = 1845 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1485947.
Up-via summary (total 1485947):.
------------------
Active 0
M1 469543
M2 864394
M3 126467
M4 20882
M5 3506
M6 983
M7 172
M8 0
M9 0
------------------
1485947
[INFO DRT-0195] Start 1st optimization iteration.
Completing 10% with 72941 violations.
elapsed time = 00:01:42, memory = 22359.21 (MB).
Completing 20% with 56039 violations.
elapsed time = 00:03:00, memory = 23111.42 (MB).
Completing 30% with 49203 violations.
elapsed time = 00:03:48, memory = 23462.17 (MB).
Completing 40% with 37493 violations.
elapsed time = 00:05:51, memory = 23797.29 (MB).
Completing 50% with 32494 violations.
elapsed time = 00:06:17, memory = 22737.40 (MB).
Completing 60% with 32494 violations.
elapsed time = 00:07:57, memory = 23749.97 (MB).
Completing 70% with 19858 violations.
elapsed time = 00:09:16, memory = 23761.67 (MB).
Completing 80% with 15360 violations.
elapsed time = 00:10:07, memory = 23808.00 (MB).
Completing 90% with 6137 violations.
elapsed time = 00:12:09, memory = 24162.86 (MB).
Completing 100% with 3126 violations.
elapsed time = 00:12:31, memory = 23044.21 (MB).
[INFO DRT-0199] Number of violations = 3592.
Viol/Layer M1 M2 M3 V3 M4 V4 M5 V5
CutSpcTbl 0 0 0 55 0 11 0 2
EOL 0 388 8 0 2 0 0 0
Metal Spacing 80 76 234 0 5 0 70 0
Recheck 6 259 183 0 18 0 0 0
Short 8 204 3 0 3 0 23 0
eolKeepOut 0 1902 38 0 11 0 3 0
[INFO DRT-0267] cpu time = 03:08:00, elapsed time = 00:12:35, memory = 22232.57 (MB), peak = 24295.54 (MB)
Total wire length = 1041540 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 296351 um.
Total wire length on LAYER M3 = 401157 um.
Total wire length on LAYER M4 = 197543 um.
Total wire length on LAYER M5 = 101650 um.
Total wire length on LAYER M6 = 30231 um.
Total wire length on LAYER M7 = 12775 um.
Total wire length on LAYER M8 = 1829 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1450472.
Up-via summary (total 1450472):.
------------------
Active 0
M1 469522
M2 841059
M3 114855
M4 20500
M5 3458
M6 941
M7 137
M8 0
M9 0
------------------
1450472
[INFO DRT-0195] Start 2nd optimization iteration.
Completing 10% with 3592 violations.
elapsed time = 00:00:33, memory = 23235.13 (MB).
Completing 20% with 3178 violations.
elapsed time = 00:00:49, memory = 23063.58 (MB).
Completing 30% with 3072 violations.
elapsed time = 00:01:04, memory = 23197.06 (MB).
Completing 40% with 2731 violations.
elapsed time = 00:01:40, memory = 23161.11 (MB).
Completing 50% with 2667 violations.
elapsed time = 00:01:43, memory = 22185.98 (MB).
Completing 60% with 2667 violations.
elapsed time = 00:02:20, memory = 22912.07 (MB).
Completing 70% with 2296 violations.
elapsed time = 00:02:35, memory = 22682.03 (MB).
Completing 80% with 2244 violations.
elapsed time = 00:02:50, memory = 22974.53 (MB).
Completing 90% with 1896 violations.
elapsed time = 00:03:25, memory = 22952.64 (MB).
Completing 100% with 1829 violations.
elapsed time = 00:03:29, memory = 22024.20 (MB).
[INFO DRT-0199] Number of violations = 2055.
Viol/Layer M1 M2 V2 M3 V3 M4 V4 M5
CutSpcTbl 0 0 0 0 11 0 4 0
EOL 0 239 0 5 0 0 0 0
Metal Spacing 45 46 0 111 0 0 0 70
Recheck 4 147 0 101 0 9 0 0
Short 1 106 1 3 0 1 0 23
eolKeepOut 0 1107 0 18 0 3 0 0
[INFO DRT-0267] cpu time = 00:51:40, elapsed time = 00:03:32, memory = 21577.52 (MB), peak = 24295.54 (MB)
Total wire length = 1040768 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 296300 um.
Total wire length on LAYER M3 = 400651 um.
Total wire length on LAYER M4 = 197368 um.
Total wire length on LAYER M5 = 101610 um.
Total wire length on LAYER M6 = 30242 um.
Total wire length on LAYER M7 = 12770 um.
Total wire length on LAYER M8 = 1824 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444203.
Up-via summary (total 1444203):.
------------------
Active 0
M1 469508
M2 838531
M3 111237
M4 20428
M5 3420
M6 945
M7 134
M8 0
M9 0
------------------
1444203
[INFO DRT-0195] Start 3rd optimization iteration.
Completing 10% with 2055 violations.
elapsed time = 00:00:14, memory = 22490.17 (MB).
Completing 20% with 1585 violations.
elapsed time = 00:00:22, memory = 22285.48 (MB).
Completing 30% with 1502 violations.
elapsed time = 00:00:27, memory = 22296.56 (MB).
Completing 40% with 1102 violations.
elapsed time = 00:00:42, memory = 22455.45 (MB).
Completing 50% with 1031 violations.
elapsed time = 00:00:44, memory = 21385.38 (MB).
Completing 60% with 1031 violations.
elapsed time = 00:00:57, memory = 22372.10 (MB).
Completing 70% with 616 violations.
elapsed time = 00:01:07, memory = 22065.98 (MB).
Completing 80% with 569 violations.
elapsed time = 00:01:13, memory = 22434.68 (MB).
Completing 90% with 228 violations.
elapsed time = 00:01:24, memory = 21470.96 (MB).
Completing 100% with 179 violations.
elapsed time = 00:01:28, memory = 21385.42 (MB).
[INFO DRT-0199] Number of violations = 179.
Viol/Layer M2 M3 V4 M5
CutSpcTbl 0 0 1 0
EOL 7 0 0 0
Metal Spacing 6 3 0 70
Short 10 0 0 22
eolKeepOut 60 0 0 0
[INFO DRT-0267] cpu time = 00:18:35, elapsed time = 00:01:28, memory = 21128.46 (MB), peak = 24295.54 (MB)
Total wire length = 1040814 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295468 um.
Total wire length on LAYER M3 = 400700 um.
Total wire length on LAYER M4 = 198245 um.
Total wire length on LAYER M5 = 101580 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444731.
Up-via summary (total 1444731):.
------------------
Active 0
M1 469508
M2 837684
M3 112621
M4 20416
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444731
[INFO DRT-0195] Start 4th optimization iteration.
Completing 10% with 179 violations.
elapsed time = 00:00:01, memory = 22022.34 (MB).
Completing 20% with 156 violations.
elapsed time = 00:00:03, memory = 21128.48 (MB).
Completing 30% with 156 violations.
elapsed time = 00:00:06, memory = 21128.48 (MB).
Completing 40% with 138 violations.
elapsed time = 00:00:07, memory = 21128.49 (MB).
Completing 50% with 138 violations.
elapsed time = 00:00:07, memory = 21128.49 (MB).
Completing 60% with 138 violations.
elapsed time = 00:00:07, memory = 21128.49 (MB).
Completing 70% with 110 violations.
elapsed time = 00:00:11, memory = 21179.44 (MB).
Completing 80% with 106 violations.
elapsed time = 00:00:15, memory = 21128.45 (MB).
Completing 90% with 99 violations.
elapsed time = 00:00:17, memory = 21128.20 (MB).
Completing 100% with 99 violations.
elapsed time = 00:00:17, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 99.
Viol/Layer M2 V4 M5
CutSpcTbl 0 1 0
EOL 1 0 0
Metal Spacing 0 0 70
Short 2 0 22
eolKeepOut 3 0 0
[INFO DRT-0267] cpu time = 00:01:51, elapsed time = 00:00:17, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040811 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295445 um.
Total wire length on LAYER M3 = 400702 um.
Total wire length on LAYER M4 = 198267 um.
Total wire length on LAYER M5 = 101576 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444688.
Up-via summary (total 1444688):.
------------------
Active 0
M1 469508
M2 837619
M3 112651
M4 20408
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444688
[INFO DRT-0195] Start 5th optimization iteration.
Completing 10% with 99 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 99 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 99 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 99 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 99 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 99 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 95 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 94 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:12, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:12, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:48, elapsed time = 00:00:12, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040809 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295441 um.
Total wire length on LAYER M3 = 400713 um.
Total wire length on LAYER M4 = 198269 um.
Total wire length on LAYER M5 = 101565 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444662.
Up-via summary (total 1444662):.
------------------
Active 0
M1 469508
M2 837606
M3 112650
M4 20396
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444662
[INFO DRT-0195] Start 6th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:41, elapsed time = 00:00:13, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040808 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295438 um.
Total wire length on LAYER M3 = 400719 um.
Total wire length on LAYER M4 = 198270 um.
Total wire length on LAYER M5 = 101559 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444649.
Up-via summary (total 1444649):.
------------------
Active 0
M1 469508
M2 837606
M3 112639
M4 20394
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444649
[INFO DRT-0195] Start 7th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:14, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:14, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:14, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:39, elapsed time = 00:00:14, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040809 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295438 um.
Total wire length on LAYER M3 = 400725 um.
Total wire length on LAYER M4 = 198271 um.
Total wire length on LAYER M5 = 101554 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444657.
Up-via summary (total 1444657):.
------------------
Active 0
M1 469508
M2 837614
M3 112641
M4 20392
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444657
[INFO DRT-0195] Start 8th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:05, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040810 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295441 um.
Total wire length on LAYER M3 = 400725 um.
Total wire length on LAYER M4 = 198269 um.
Total wire length on LAYER M5 = 101553 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444745.
Up-via summary (total 1444745):.
------------------
Active 0
M1 469508
M2 837678
M3 112659
M4 20398
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444745
[INFO DRT-0195] Start 9th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:22, elapsed time = 00:00:06, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040809 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295443 um.
Total wire length on LAYER M3 = 400725 um.
Total wire length on LAYER M4 = 198266 um.
Total wire length on LAYER M5 = 101553 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444721.
Up-via summary (total 1444721):.
------------------
Active 0
M1 469508
M2 837666
M3 112653
M4 20392
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444721
[INFO DRT-0195] Start 10th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:40, elapsed time = 00:00:09, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040807 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295440 um.
Total wire length on LAYER M3 = 400727 um.
Total wire length on LAYER M4 = 198268 um.
Total wire length on LAYER M5 = 101551 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444643.
Up-via summary (total 1444643):.
------------------
Active 0
M1 469508
M2 837612
M3 112637
M4 20384
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444643
[INFO DRT-0195] Start 11th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:43, elapsed time = 00:00:09, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040807 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295439 um.
Total wire length on LAYER M3 = 400727 um.
Total wire length on LAYER M4 = 198268 um.
Total wire length on LAYER M5 = 101551 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444637.
Up-via summary (total 1444637):.
------------------
Active 0
M1 469508
M2 837610
M3 112635
M4 20382
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444637
[INFO DRT-0195] Start 12th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:42, elapsed time = 00:00:10, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040807 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295438 um.
Total wire length on LAYER M3 = 400725 um.
Total wire length on LAYER M4 = 198269 um.
Total wire length on LAYER M5 = 101553 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444637.
Up-via summary (total 1444637):.
------------------
Active 0
M1 469508
M2 837598
M3 112641
M4 20388
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444637
[INFO DRT-0195] Start 13th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:40, elapsed time = 00:00:13, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040808 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295436 um.
Total wire length on LAYER M3 = 400725 um.
Total wire length on LAYER M4 = 198271 um.
Total wire length on LAYER M5 = 101554 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444639.
Up-via summary (total 1444639):.
------------------
Active 0
M1 469508
M2 837602
M3 112639
M4 20388
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444639
[INFO DRT-0195] Start 14th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:15, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:15, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:15, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:40, elapsed time = 00:00:15, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040806 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295435 um.
Total wire length on LAYER M3 = 400723 um.
Total wire length on LAYER M4 = 198271 um.
Total wire length on LAYER M5 = 101556 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444645.
Up-via summary (total 1444645):.
------------------
Active 0
M1 469508
M2 837606
M3 112639
M4 20390
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444645
[INFO DRT-0195] Start 15th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:05, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040806 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295435 um.
Total wire length on LAYER M3 = 400722 um.
Total wire length on LAYER M4 = 198271 um.
Total wire length on LAYER M5 = 101556 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444657.
Up-via summary (total 1444657):.
------------------
Active 0
M1 469508
M2 837614
M3 112643
M4 20390
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444657
[INFO DRT-0195] Start 16th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:22, elapsed time = 00:00:05, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040805 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295437 um.
Total wire length on LAYER M3 = 400722 um.
Total wire length on LAYER M4 = 198268 um.
Total wire length on LAYER M5 = 101556 um.
Total wire length on LAYER M6 = 30239 um.
Total wire length on LAYER M7 = 12757 um.
Total wire length on LAYER M8 = 1823 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444659.
Up-via summary (total 1444659):.
------------------
Active 0
M1 469508
M2 837626
M3 112635
M4 20388
M5 3428
M6 940
M7 134
M8 0
M9 0
------------------
1444659
[INFO DRT-0195] Start 17th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 96 violations.
elapsed time = 00:00:12, memory = 21128.20 (MB).
Completing 90% with 96 violations.
elapsed time = 00:00:12, memory = 21128.20 (MB).
Completing 100% with 96 violations.
elapsed time = 00:00:12, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 96.
Viol/Layer M4 M5
EOL 1 0
Metal Spacing 0 70
Short 0 22
eolKeepOut 3 0
[INFO DRT-0267] cpu time = 00:00:46, elapsed time = 00:00:12, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040777 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295306 um.
Total wire length on LAYER M3 = 400871 um.
Total wire length on LAYER M4 = 198393 um.
Total wire length on LAYER M5 = 101394 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444622.
Up-via summary (total 1444622):.
------------------
Active 0
M1 469508
M2 837500
M3 112789
M4 20318
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444622
[INFO DRT-0195] Start 18th optimization iteration.
Completing 10% with 96 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 96 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 96 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 96 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 96 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 96 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 96 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:39, elapsed time = 00:00:08, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040777 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295306 um.
Total wire length on LAYER M3 = 400869 um.
Total wire length on LAYER M4 = 198393 um.
Total wire length on LAYER M5 = 101396 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444630.
Up-via summary (total 1444630):.
------------------
Active 0
M1 469508
M2 837510
M3 112783
M4 20322
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444630
[INFO DRT-0195] Start 19th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 92 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 92 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 92 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 80% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 90% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 100% with 92 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 92.
Viol/Layer M5
Metal Spacing 70
Short 22
[INFO DRT-0267] cpu time = 00:00:42, elapsed time = 00:00:09, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040777 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295306 um.
Total wire length on LAYER M3 = 400869 um.
Total wire length on LAYER M4 = 198393 um.
Total wire length on LAYER M5 = 101396 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444626.
Up-via summary (total 1444626):.
------------------
Active 0
M1 469508
M2 837506
M3 112783
M4 20322
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444626
[INFO DRT-0195] Start 20th optimization iteration.
Completing 10% with 92 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 87 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 83 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 83 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 83 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 83 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 82 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 81 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 90% with 81 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 100% with 81 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 81.
Viol/Layer M5
Metal Spacing 62
Short 19
[INFO DRT-0267] cpu time = 00:00:40, elapsed time = 00:00:10, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040783 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295306 um.
Total wire length on LAYER M3 = 400871 um.
Total wire length on LAYER M4 = 198399 um.
Total wire length on LAYER M5 = 101394 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444630.
Up-via summary (total 1444630):.
------------------
Active 0
M1 469508
M2 837508
M3 112785
M4 20322
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444630
[INFO DRT-0195] Start 21st optimization iteration.
Completing 10% with 81 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 81 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 77 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 77 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 77 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 77 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 77 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 74 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 90% with 74 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 100% with 74 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 74.
Viol/Layer M5
Metal Spacing 55
Short 19
[INFO DRT-0267] cpu time = 00:00:36, elapsed time = 00:00:10, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040778 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295306 um.
Total wire length on LAYER M3 = 400867 um.
Total wire length on LAYER M4 = 198395 um.
Total wire length on LAYER M5 = 101398 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444628.
Up-via summary (total 1444628):.
------------------
Active 0
M1 469508
M2 837504
M3 112783
M4 20326
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444628
[INFO DRT-0195] Start 22nd optimization iteration.
Completing 10% with 74 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 73 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 73 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 73 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 73 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 73 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 73 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 72 violations.
elapsed time = 00:00:11, memory = 21128.20 (MB).
Completing 90% with 72 violations.
elapsed time = 00:00:11, memory = 21128.20 (MB).
Completing 100% with 72 violations.
elapsed time = 00:00:11, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 72.
Viol/Layer M5
Metal Spacing 53
Short 19
[INFO DRT-0267] cpu time = 00:00:30, elapsed time = 00:00:11, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040778 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295307 um.
Total wire length on LAYER M3 = 400868 um.
Total wire length on LAYER M4 = 198393 um.
Total wire length on LAYER M5 = 101397 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444642.
Up-via summary (total 1444642):.
------------------
Active 0
M1 469508
M2 837516
M3 112785
M4 20326
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444642
[INFO DRT-0195] Start 23rd optimization iteration.
Completing 10% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 50% with 72 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 72 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 72 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 72 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 90% with 72 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 100% with 72 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 72.
Viol/Layer M5
Metal Spacing 53
Short 19
[INFO DRT-0267] cpu time = 00:00:12, elapsed time = 00:00:04, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040779 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295309 um.
Total wire length on LAYER M3 = 400868 um.
Total wire length on LAYER M4 = 198392 um.
Total wire length on LAYER M5 = 101397 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444664.
Up-via summary (total 1444664):.
------------------
Active 0
M1 469508
M2 837532
M3 112787
M4 20330
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444664
[INFO DRT-0195] Start 24th optimization iteration.
Completing 10% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 72 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 72 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 90% with 70 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 100% with 70 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 70.
Viol/Layer M5
Metal Spacing 52
Short 18
[INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:04, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040779 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295310 um.
Total wire length on LAYER M3 = 400870 um.
Total wire length on LAYER M4 = 198391 um.
Total wire length on LAYER M5 = 101395 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12755 um.
Total wire length on LAYER M8 = 1820 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444664.
Up-via summary (total 1444664):.
------------------
Active 0
M1 469508
M2 837546
M3 112781
M4 20322
M5 3433
M6 940
M7 134
M8 0
M9 0
------------------
1444664
[INFO DRT-0195] Start 25th optimization iteration.
Completing 10% with 70 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 70 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 70 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 40% with 71 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 50% with 75 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 75 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 80 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 80 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 90% with 85 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 100% with 87 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 87.
Viol/Layer M4 M5
Metal Spacing 0 61
Short 1 22
eolKeepOut 3 0
[INFO DRT-0267] cpu time = 00:00:28, elapsed time = 00:00:09, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040775 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295289 um.
Total wire length on LAYER M3 = 400881 um.
Total wire length on LAYER M4 = 198412 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444673.
Up-via summary (total 1444673):.
------------------
Active 0
M1 469508
M2 837523
M3 112798
M4 20333
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444673
[INFO DRT-0195] Start 26th optimization iteration.
Completing 10% with 87 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 80 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 75 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 40% with 75 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 50% with 75 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 75 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 54 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 49 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 90% with 49 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 100% with 49 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 49.
Viol/Layer M5
Metal Spacing 38
Short 11
[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:06, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040775 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295287 um.
Total wire length on LAYER M3 = 400881 um.
Total wire length on LAYER M4 = 198413 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444669.
Up-via summary (total 1444669):.
------------------
Active 0
M1 469508
M2 837521
M3 112798
M4 20331
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444669
[INFO DRT-0195] Start 27th optimization iteration.
Completing 10% with 49 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 47 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 46 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 40% with 46 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 50% with 46 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 60% with 46 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 70% with 44 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 80% with 43 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 90% with 43 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 100% with 43 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 43.
Viol/Layer M5
Metal Spacing 35
Short 8
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:06, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040776 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295288 um.
Total wire length on LAYER M3 = 400882 um.
Total wire length on LAYER M4 = 198413 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444667.
Up-via summary (total 1444667):.
------------------
Active 0
M1 469508
M2 837519
M3 112798
M4 20331
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444667
[INFO DRT-0195] Start 28th optimization iteration.
Completing 10% with 43 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 43 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 42 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 40% with 42 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 50% with 42 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 42 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 40 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 80% with 40 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 90% with 40 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 100% with 40 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 40.
Viol/Layer M5
Metal Spacing 32
Short 8
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:05, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040776 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295288 um.
Total wire length on LAYER M3 = 400882 um.
Total wire length on LAYER M4 = 198413 um.
Total wire length on LAYER M5 = 101381 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444667.
Up-via summary (total 1444667):.
------------------
Active 0
M1 469508
M2 837519
M3 112796
M4 20333
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444667
[INFO DRT-0195] Start 29th optimization iteration.
Completing 10% with 40 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 40 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 40 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 40% with 40 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 50% with 40 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 60% with 40 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 70% with 40 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 40 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 90% with 40 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 100% with 40 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 40.
Viol/Layer M5
Metal Spacing 32
Short 8
[INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:08, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040777 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295288 um.
Total wire length on LAYER M3 = 400881 um.
Total wire length on LAYER M4 = 198414 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444675.
Up-via summary (total 1444675):.
------------------
Active 0
M1 469508
M2 837523
M3 112796
M4 20337
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444675
[INFO DRT-0195] Start 30th optimization iteration.
Completing 10% with 40 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 38 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 38 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 40% with 38 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 50% with 38 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 60% with 38 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 70% with 38 violations.
elapsed time = 00:00:08, memory = 21128.20 (MB).
Completing 80% with 36 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 90% with 36 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 100% with 36 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 36.
Viol/Layer M5
Metal Spacing 29
Short 7
[INFO DRT-0267] cpu time = 00:00:26, elapsed time = 00:00:13, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040778 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295289 um.
Total wire length on LAYER M3 = 400882 um.
Total wire length on LAYER M4 = 198414 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444677.
Up-via summary (total 1444677):.
------------------
Active 0
M1 469508
M2 837525
M3 112796
M4 20337
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444677
[INFO DRT-0195] Start 31st optimization iteration.
Completing 10% with 36 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 36 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 36 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 36 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 35 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 35 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 90% with 35 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 100% with 35 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 35.
Viol/Layer M5
Metal Spacing 28
Short 7
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040779 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295292 um.
Total wire length on LAYER M3 = 400882 um.
Total wire length on LAYER M4 = 198412 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444683.
Up-via summary (total 1444683):.
------------------
Active 0
M1 469508
M2 837533
M3 112794
M4 20337
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444683
[INFO DRT-0195] Start 32nd optimization iteration.
Completing 10% with 35 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 35 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 35 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 35 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 50% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 80% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 90% with 35 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 100% with 35 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 35.
Viol/Layer M5
Metal Spacing 28
Short 7
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:05, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040779 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295292 um.
Total wire length on LAYER M3 = 400882 um.
Total wire length on LAYER M4 = 198412 um.
Total wire length on LAYER M5 = 101382 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444683.
Up-via summary (total 1444683):.
------------------
Active 0
M1 469508
M2 837533
M3 112794
M4 20337
M5 3437
M6 940
M7 134
M8 0
M9 0
------------------
1444683
[INFO DRT-0195] Start 33rd optimization iteration.
Completing 10% with 35 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 36 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 36 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 43 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 50% with 43 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 60% with 43 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 70% with 44 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 80% with 44 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 90% with 63 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 100% with 63 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 63.
Viol/Layer V3 M4 M5
CutSpcTbl 3 0 0
EOL 0 5 0
Metal Spacing 0 1 25
Short 0 3 2
eolKeepOut 0 24 0
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:04, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040778 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295290 um.
Total wire length on LAYER M3 = 400897 um.
Total wire length on LAYER M4 = 198413 um.
Total wire length on LAYER M5 = 101367 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444739.
Up-via summary (total 1444739):.
------------------
Active 0
M1 469508
M2 837549
M3 112829
M4 20340
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444739
[INFO DRT-0195] Start 34th optimization iteration.
Completing 10% with 63 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 56 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 43 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 40% with 43 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 50% with 43 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 60% with 43 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 70% with 39 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 29 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 90% with 29 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 100% with 29 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 29.
Viol/Layer V3 M4 M5
CutSpcTbl 1 0 0
EOL 0 1 0
Metal Spacing 0 0 20
Short 0 0 4
eolKeepOut 0 3 0
[INFO DRT-0267] cpu time = 00:00:14, elapsed time = 00:00:06, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040782 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295289 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198418 um.
Total wire length on LAYER M5 = 101365 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444723.
Up-via summary (total 1444723):.
------------------
Active 0
M1 469508
M2 837535
M3 112829
M4 20338
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444723
[INFO DRT-0195] Start 35th optimization iteration.
Completing 10% with 29 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 25 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 25 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 40% with 25 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 50% with 25 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 60% with 25 violations.
elapsed time = 00:00:03, memory = 21128.20 (MB).
Completing 70% with 25 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 24 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 90% with 24 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 100% with 24 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 24.
Viol/Layer M5
Metal Spacing 20
Short 4
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:07, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040780 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295290 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198415 um.
Total wire length on LAYER M5 = 101365 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444717.
Up-via summary (total 1444717):.
------------------
Active 0
M1 469508
M2 837537
M3 112819
M4 20340
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444717
[INFO DRT-0195] Start 36th optimization iteration.
Completing 10% with 24 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 24 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 30% with 24 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 24 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 24 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 24 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 24 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 80% with 23 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 90% with 23 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
Completing 100% with 23 violations.
elapsed time = 00:00:10, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 23.
Viol/Layer M5
Metal Spacing 19
Short 4
[INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:10, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040781 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295290 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198415 um.
Total wire length on LAYER M5 = 101365 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444715.
Up-via summary (total 1444715):.
------------------
Active 0
M1 469508
M2 837535
M3 112821
M4 20338
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444715
[INFO DRT-0195] Start 37th optimization iteration.
Completing 10% with 23 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 23 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 23 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 40% with 23 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 50% with 23 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 60% with 23 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 70% with 23 violations.
elapsed time = 00:00:07, memory = 21128.20 (MB).
Completing 80% with 23 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 90% with 23 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
Completing 100% with 23 violations.
elapsed time = 00:00:13, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 23.
Viol/Layer M4 M5
Metal Spacing 0 18
Short 2 3
[INFO DRT-0267] cpu time = 00:00:25, elapsed time = 00:00:13, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040782 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295291 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198415 um.
Total wire length on LAYER M5 = 101366 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444725.
Up-via summary (total 1444725):.
------------------
Active 0
M1 469508
M2 837545
M3 112819
M4 20340
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444725
[INFO DRT-0195] Start 38th optimization iteration.
Completing 10% with 23 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 22 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 40% with 22 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 50% with 22 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 60% with 22 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
Completing 70% with 22 violations.
elapsed time = 00:00:05, memory = 21128.20 (MB).
Completing 80% with 22 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 90% with 22 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
Completing 100% with 22 violations.
elapsed time = 00:00:09, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 22.
Viol/Layer M5
Metal Spacing 18
Short 4
[INFO DRT-0267] cpu time = 00:00:19, elapsed time = 00:00:09, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040781 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295291 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198415 um.
Total wire length on LAYER M5 = 101365 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444719.
Up-via summary (total 1444719):.
------------------
Active 0
M1 469508
M2 837539
M3 112821
M4 20338
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444719
[INFO DRT-0195] Start 39th optimization iteration.
Completing 10% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 50% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 80% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 90% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 100% with 22 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 22.
Viol/Layer M5
Metal Spacing 18
Short 4
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040782 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295292 um.
Total wire length on LAYER M3 = 400898 um.
Total wire length on LAYER M4 = 198414 um.
Total wire length on LAYER M5 = 101365 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444725.
Up-via summary (total 1444725):.
------------------
Active 0
M1 469508
M2 837545
M3 112819
M4 20340
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444725
[INFO DRT-0195] Start 40th optimization iteration.
Completing 10% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 30% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 40% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 50% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 22 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 22 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 22 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 90% with 22 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 100% with 22 violations.
elapsed time = 00:00:04, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 22.
Viol/Layer M5
Metal Spacing 18
Short 4
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:04, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040781 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295292 um.
Total wire length on LAYER M3 = 400899 um.
Total wire length on LAYER M4 = 198413 um.
Total wire length on LAYER M5 = 101364 um.
Total wire length on LAYER M6 = 30235 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444721.
Up-via summary (total 1444721):.
------------------
Active 0
M1 469508
M2 837539
M3 112825
M4 20336
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444721
[INFO DRT-0195] Start 41st optimization iteration.
Completing 10% with 22 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 30% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 40% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 50% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 60% with 35 violations.
elapsed time = 00:00:01, memory = 21128.20 (MB).
Completing 70% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 80% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 90% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
Completing 100% with 70 violations.
elapsed time = 00:00:02, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 70.
Viol/Layer M3 V3 M4 M5
CutSpcTbl 0 1 0 0
EOL 0 0 7 0
Metal Spacing 0 0 3 9
Short 1 1 9 0
eolKeepOut 0 0 39 0
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:02, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040783 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295296 um.
Total wire length on LAYER M3 = 400904 um.
Total wire length on LAYER M4 = 198412 um.
Total wire length on LAYER M5 = 101359 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444757.
Up-via summary (total 1444757):.
------------------
Active 0
M1 469508
M2 837565
M3 112833
M4 20338
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444757
[INFO DRT-0195] Start 42nd optimization iteration.
Completing 10% with 70 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 66 violations.
elapsed time = 00:01:23, memory = 21128.20 (MB).
Completing 30% with 53 violations.
elapsed time = 00:02:13, memory = 21128.20 (MB).
Completing 40% with 53 violations.
elapsed time = 00:02:13, memory = 21128.20 (MB).
Completing 50% with 53 violations.
elapsed time = 00:02:13, memory = 21128.20 (MB).
Completing 60% with 53 violations.
elapsed time = 00:02:13, memory = 21128.20 (MB).
Completing 70% with 48 violations.
elapsed time = 00:02:15, memory = 21128.20 (MB).
Completing 80% with 39 violations.
elapsed time = 00:02:18, memory = 21128.20 (MB).
Completing 90% with 39 violations.
elapsed time = 00:02:18, memory = 21128.20 (MB).
Completing 100% with 39 violations.
elapsed time = 00:02:18, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 39.
Viol/Layer V3 M4 M5
CutSpcTbl 1 0 0
EOL 0 3 0
Metal Spacing 0 2 16
Short 0 2 3
eolKeepOut 0 12 0
[INFO DRT-0267] cpu time = 00:03:00, elapsed time = 00:02:18, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040781 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295292 um.
Total wire length on LAYER M3 = 400904 um.
Total wire length on LAYER M4 = 198414 um.
Total wire length on LAYER M5 = 101359 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444741.
Up-via summary (total 1444741):.
------------------
Active 0
M1 469508
M2 837559
M3 112827
M4 20334
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444741
[INFO DRT-0195] Start 43rd optimization iteration.
Completing 10% with 39 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 28 violations.
elapsed time = 00:00:06, memory = 21128.20 (MB).
Completing 30% with 28 violations.
elapsed time = 00:00:20, memory = 21128.20 (MB).
Completing 40% with 28 violations.
elapsed time = 00:00:20, memory = 21128.20 (MB).
Completing 50% with 28 violations.
elapsed time = 00:00:20, memory = 21128.20 (MB).
Completing 60% with 28 violations.
elapsed time = 00:00:20, memory = 21128.20 (MB).
Completing 70% with 28 violations.
elapsed time = 00:00:24, memory = 21128.20 (MB).
Completing 80% with 28 violations.
elapsed time = 00:00:28, memory = 21128.20 (MB).
Completing 90% with 28 violations.
elapsed time = 00:00:28, memory = 21128.20 (MB).
Completing 100% with 28 violations.
elapsed time = 00:00:28, memory = 21128.20 (MB).
[INFO DRT-0199] Number of violations = 28.
Viol/Layer M4 M5
EOL 1 0
Metal Spacing 1 18
Short 1 4
eolKeepOut 3 0
[INFO DRT-0267] cpu time = 00:00:42, elapsed time = 00:00:28, memory = 21128.20 (MB), peak = 24295.54 (MB)
Total wire length = 1040782 um.
Total wire length on LAYER M1 = 0 um.
Total wire length on LAYER M2 = 295293 um.
Total wire length on LAYER M3 = 400903 um.
Total wire length on LAYER M4 = 198414 um.
Total wire length on LAYER M5 = 101361 um.
Total wire length on LAYER M6 = 30234 um.
Total wire length on LAYER M7 = 12756 um.
Total wire length on LAYER M8 = 1819 um.
Total wire length on LAYER M9 = 0 um.
Total wire length on LAYER Pad = 0 um.
Total number of vias = 1444731.
Up-via summary (total 1444731):.
------------------
Active 0
M1 469508
M2 837555
M3 112819
M4 20336
M5 3439
M6 940
M7 134
M8 0
M9 0
------------------
1444731
[INFO DRT-0195] Start 44th optimization iteration.
Completing 10% with 28 violations.
elapsed time = 00:00:00, memory = 21128.20 (MB).
Completing 20% with 28 violations.
elapsed time = 00:05:30, memory = 21128.20 (MB).
Completing 30% with 28 violations.
elapsed time = 00:07:16, memory = 21128.20 (MB).
Completing 40% with 28 violations.
elapsed time = 00:07:16, memory = 21128.20 (MB).
Completing 50% with 28 violations.
elapsed time = 00:07:16, memory = 21128.20 (MB).
Completing 60% with 28 violations.
elapsed time = 00:07:16, memory = 21128.20 (MB).
Completing 70% with 28 violations.
elapsed time = 00:07:17, memory = 21128.20 (MB).
[did not observe the run any further]
add_pdn_ring -grid {top} -layers {M5 M6} -widths {0.504 0.544} -spacings {0.096} -core_offset {0.504}
leads to rings outside the core area are there isn't enough room to put the rings between the core and die areas:
You'll either need to adjust the rings or the floorplan (or both).
You'll either need to adjust the rings or the floorplan (or both).
Thanks!
Is there a reason there cant be an actionable error message here?
@maliberty With CORE_UTILIZATION=30, there is no way to adjust the amount of space between the core area and the die area, this is done automatically.
Shouldn't the spacing be adjusted to a legal amount automatically?
You set it through CORE_MARGIN
Thanks!
Feature request: an actionable error message. "Error: No space for power ring, increase CORE_MARGIN"
(or the openroad speak equivalent from where the user should be able to figure out CORE_MARGIN)
@maliberty Tested some more.
Long story short: This is issue is now a feature request for adding an actionable error message when the PDN ring doesn't fit.
How come the pins were placed overlapping the power straps? That seems to be the actual issue here based on my read of this.
How come the pins were placed overlapping the power straps? That seems to be the actual issue here based on my read of this.
Because CORE_MARGIN, CORE/DIE_AREA doesn't leave enough room for the power ring. The error message will tell you at the floorplanning stage so as to avoid having to wait all the way to routing before discovering this.
@oharboe that doesn't explain why PPL put in the pins on top of the straps
What is PPL?
Pins are added before the PDN in ORFS.
If the pins are marked FIXED then PDN will avoid them, if they are just PLACED then PDN is expecting a second call to the pin placer tool (PPL) to place them properly.
If the pins are marked FIXED then PDN will avoid them, if they are just PLACED then PDN is expecting a second call to the pin placer tool (PPL) to place them properly.
So... more things to investigate...
Still seems like a good idea to have an error message if the PDN ring can't be placed inside the die area...
@oharboe sure, I don't disagree (I just think the implementation in the PR is not quite consistent with the rest of the codebase), I generally don't like that PDN places shaped outside the DIE area, but OpenLANE relies on this behavior.
I'm guessing that ppl doesn't look for obstructions on the die edge as there generally aren't any (@eder-matheus is that right?). Even if it did put the pins off the straps, they would not be on the edge of the block anymore which wouldn't be good. You would have to access them from above which doesn't make sense.
I don't know about what OL is doing with such stripes. Would you say more.
@maliberty PPL actually looks for obstructions, but I believe only placement obstructions. We iterate through them using this for loop:
for (odb::dbObstruction* obstruction : getBlock()->getObstructions()) {
I could extend this function to iterate through PDN shapes and ensure that PPL will not use tracks that overlap with these nets.
@eder-matheus those are routing obstructions rather than placement blockages. I'm not sure this usage makes sense. Let's see how the discussion concludes before doing any work.
@eder-matheus those are routing obstructions rather than placement blockages. I'm not sure this usage makes sense. Let's see how the discussion concludes before doing any work.
Yes, you're right. The code I've mentioned is not used, but we do consider macros to avoid using tracks that would be blocked by them.