[soc_rcm] fix instruction re-ordering when reading periph clocks

[cmattatall]

On -O2 and -O3, instruction re-ordering of non-volatile accesses to peripheral clock div registers sometimes get interleaved depending on inlining

// inside SOC_rcmSetPeripheralClock

 *ptrClkSrcReg = SOC_rcmInsert16 (*ptrClkSrcReg, 11U, 0U, clkSrcVal); // expression 1
  while(CSL_REG32_RD(ptrClkSrcReg) != clkSrcVal) // expression 2
  {;}
      
  // This PR prevents re-ordering of expressions 1 and 2