Support Intel APX

[mazegen]

Something to keep an eye on, for future UASM releases.

https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html

Intel APX doubles the number of general-purpose registers (GPRs) from 16 to 32.

New REX2 prefix provides uniform access to the new registers across the legacy integer instruction set. Intel AVX instructions gain access via new bits defined in the existing EVEX prefix. In addition, legacy integer instructions now can also use EVEX to encode a dedicated destination register operand – turning them into three-operand instructions and reducing the need for extra register move instructions.

We are adding PUSH2/POP2 instructions that transfer two register values within a single memory operation.

Intel APX adds conditional forms of load, store, and compare/test instructions, and it also adds an option for the compiler to suppress the status flags writes of common instructions.