PeakRDL-uvm
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SystemRDL
Generate UVM register model from compiled SystemRDL input
Your code is very impressive, but could you please tell me how to generate Verilog files?
This PR adds factory registration for register blocks. UVM encourages registering component and object classes with the factory. While it's not necessary to register *all* classes (eg individual registers), registering...
In some projects it may be useful to generate a full SoC UVM output and also multiple Block Level outputs. I have tried this and, with the default options, the...
See example in https://github.com/SystemRDL/systemrdl-compiler/issues/193 Current implementation will silently emit colliding output, or even reuse an incorrect typedef. Monitor for this and emit an error if it occurs. Ideas for fix:...
Currently, there isn't really a well-defined mechanism to augment the generated UVM code. Refactor the template scheme to provide "official" mechanisms that allow users to augment the generated UVM. This...
Currently donttest/doncompare is not supported. Map this to UVM concepts
The UVM 1.2 user guide outlines very specific recommendations on what a register model shall contain, how it should be structured, etc. Current version does not follow these recommendations very...
Add a mechanism that allows users to split a system's UVM register model into multiple files. Goal is to allow top-level verification environments to re-use the register model components from...
Currently, a `uvm_vreg` is unconditionally used whenever an RDL `reg` is instantiated within a `mem`. Add better user control over this: * Disable use of `uvm_vreg` if desired * Only...
Currently, the UVM exporter does nothing to protect the generated output from using restricted SystemVerilog keywords. Add a keyword filter, similar to what was done for the `regblock` generator: https://github.com/SystemRDL/PeakRDL-regblock/blob/main/src/peakrdl_regblock/identifier_filter.py