Drawing the cache architecture

[SoCScholar]

Hi charles,

I am wondering about drawing the diagram of a cache architecture for my own purpose.

Could you please let me know how it is organized?

1. L1 cache WB counter
2. L1 cache refill counter
3. inclusive nature of L1 and L2. how they interplay during line eviction and update.
4. coherency nature of cache like WB cache policy, cache eviction, etc.
5. L2 cache architecture.
6. Main Memory.

I will draw it according to your suggestion and explanation. I will post here also :).

Something like this for documentation so it will be easier for reader too

Write-back (WB) https://developer.arm.com/documentation/den0024/a/Caches/Cache-policies

Cache configuration

https://developer.arm.com/documentation/den0024/a/The-Memory-Management-Unit/Translation-tables-in-ARMv8-A/Cache-configuration

Inclusive and exclusive caches https://developer.arm.com/documentation/den0024/a/Caches/Cache-terminology/Inclusive-and-exclusive-caches

Thank you < 3

[Dolu1990]

Hi,

L1 cache WB counter

That's in the Scope peripheral outside the CPU, with one wire from the CPU L1 to count up on cache writeback start event

L1 cache refill counter

same but on cache refill counter

inclusive nature of L1 and L2. how they interplay during line eviction and update.

L1 and L2 are inclusive yes. The L2 has a eviction buffer, so an eviction triggered from a refill will not block anything.

coherency nature of cache like WB cache policy, cache eviction, etc.

L1 is a write back cache, only one l1 cache is allowed to have a dirty copy of a given memory block. When another cache want write permitions, then the L2 dictionnary ensure that there is no other L1 with dirty data. Dirty L1 data which are written back into the L2 aren't written back to the main memory until the L2 itself need to make some room.

L2 cache architecture.

here is some doc : https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/Pipeline/introduction.html

Main Memory.

? that's just a tilelink non coherent bus.