NaxRiscv

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about litex and dhrystone

41

Hi,dear dolu, I am currently learning how to use the kernel generated by Litex to run the dhrystone algorithm on SOC. The specific operation is: 1. Generate a SOC system...

duanjiulon

Dear Charles, Is it how L1 cache and CPU communicate during Load/store ? **Pipeline: FetchCachePlugin** **Pipeline: DataCachePlugin**

SoCScholar

how to run a nax_core with a AXI4 interface

24

1.Hello, prior to this, I successfully ran a nax_soc using lite according to your tutorial, but its nax_core core interface is AXI4_lite. I want to use AXI, but I entered...

duanjiulon

The mmu_sv39.elf fail with SocSim

18

Hi Charles, The mmu_sv39.elf fail with SocSim, here is the command I used ```Bash sbt "runMain naxriscv.platform.tilelinkdemo.SocSim --xlen 64 --nax-count 1 --load-elf ext/NaxSoftware/baremetal/mmu_sv39/build/rv64ima/mmu_sv39.elf --start-symbol _start --pass-symbol pass --trace" ``` According...

Bill94l

Some guidance on better timing

3

Hi there, I'm using your CPU in a quad core constellation on a nexys video. The SoC was generated with: ``` python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --bus-standard axi-lite \ --with-video-framebuffer --with-coherent-dma...

tristanitschner

Request for Guidance: Starting with a Minimal Framework

10

Hi, I've been working with SpinalHDL for a few months and am inspired by the design of NaxRiscv. I aim to deepen my understanding by building a toy CPU from...

skylayer

Error in implementation of SRAW and SRAIW instructions

3

Hi, I found inconsistent results when using the shift instructions sraw and sraiw. These 64-bit-specific instructions perform the shift on the right-hand 32-bit part of the word and propagate the...

Nanotrust

 https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/litex/NaxSoc.scala#L76 Dear charles, If I understand correctly, I've managed to derive a diagram from the provided code. I'm curious about how Memfilter communicates with L2 cache, specifically, the interfaces...

SoCScholar

Changing Naxriscv instructions - command

1

Hi, I am a starter in this code and would like to initially change some Naxriscv instructions. To provide some context, I was able to successfully compile and run litex,...

mdmriscv

L1/L2 cache and integration with CPU pipeline

2

Hi charles, I have some doubt regarding L1 and L2 cache sets and cache line in each set of L1 and L2 data cache. can you please help me to...

SoCScholar