e200_opensource
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SI-RISCV
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Hello, I am running Verilog simulate testbench according to Chapter 17 of the book, but a fault occurred that ```sh $make run_test ... cd rv32ui-p-add; echo "Test Result Summary: PASS"...
你好，请问在蜂鸟的处理器e203中是否使用了RAS技术？我查看了蜂鸟的那本书，和rtl代码，并未找到相应的技术使用。 如果要是想使用RAS技术，是不是需要考虑编译器方面的问题？
Add a define for the address width and replace the hardcoded number with it. Also fix the width on EAI CSR registers.
There is combination loop in icb_claim_irq and icb_complete_irq assign logic. This loop will make the simulation tool time stuck(the tool is ncsim), and lint/synthesize can't found this loop. After analysis,...
about JTAG and flash has its problems~
Modules accessed through DTM are chip selected based only on DTM address field. In case of Debug RAM, the other control signal is RD (read/not write). RD maps to DTM...
