nmigen-tutorial

nmigen-tutorial copied to clipboard

from typing import List from nmigen import * from nmigen.back.pysim import Simulator, Delay, Settle from nmigen import Elaboratable,Module,Signal from nmigen.build import Platform from nmigen.cli import main_parser,main_runner class Adder(Elaboratable): def __init__(self):...

mayank-kabra2001

I don't know why anyone would want to do this, but I _did_ get Yosys and nMigen installed on my ARM Mac. If anyone is interested, I can probably write...

sunipkm

Confusing explanation about signal width

1

In [`6_combining.md`](https://github.com/RobertBaruch/nmigen-tutorial/blob/master/6_combining.md) there is a slightly confusing explanation: > Here, `a+b` must be a 17-bit signal because in Python, integers are as wide as they need to be. Please correct...

DurandA

examples for Fomu?

1

I'm interested in getting some nMigen examples for the Fomu workshop site. @mithro suggested I asked you. Have you tried out these examples with the Fomu? Thanks!

pdp7