RV12
RV12 copied to clipboard
RoaLogic
RISC-V CPU Core
Did you implement the DAP [ Debug Access Port ] what is protocol compatible with your debug control : SWD or JTAG ?
Hello, I am trying to synthesize the core but I get the above error, I am using Xilinx Vivado and my board is a Artyx 7 I am quite new...
can't run the simulation with vcs, the command is only: "make SIM=vcs", guess the command is this the log is like this: - RISC-V Regression Testbench ----------- `---' ---------- XLEN...
It seems you only increment minstret when wb_bubble is low. But a BEQ raises wb_bubble, so you don't count it. Is this the intended behavior? 
As this core is targeting embedded market, I'd like to know if there's anything special in interrupt handling (context saving/restore) comparing mainstream RV cores which seems mainly for MPU area....
--atx-headers, --base-header-level, and -t markdown_github were deprecated, with --atx-headers being incompatible with, pandoc starting with version 3.0. I changed the compile.sh to use the updated equivalent flags.
