VHDL-Mode
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Remillard
A package for Sublime Text that aids coding in the VHDL language.
VHDL-2002 and VHDL-2008 defined a thread-safe, object-oriented type called "protected" type. Please refer to the VHDL LRM. An example source that has protected-type issues with Sublime Text, but compiles for...
It would be nice to get automatic indent after some structures like "then" and so forth. Typing in this mode and having to hit tab a lot has a strange...
Found this happening, not sure why it's happening and not a lot of time to debug at the moment: ``` entity asdf is port ( ); end entity asdf; entity...
I am supposed to be able to copy a port list from a component declaration however the following did not work (and it effectively scrolled up until it found the...
Should start to think about extending syntax to 2019 standard. Sigasi has a grammar document handy at https://insights.sigasi.com/tags/ebnf/
Something like: ``` procedure check_val (expected : in std_logic_vector; actual : in std_logic_vector; file out_stream : text; debug : in boolean := TRUE ) is ``` will throw an exception...
Accessing a fully qualified signal name from a lower hierarchy is not scoped: Example: `` represents the signal in the DUT instance one lower down from the testbench but the...
Just found this oddity: ``` dword_count := 0; bit_count := 0; DATA_FILLLER_G00 : while (bits
It'd be kind of nice to be able to select a comment region and reflow to the EOL margin (as set by user preferences.)
The parenthesis in an `if` conditional is scoped as follows (for example): ``` vhdl-mode: source.vhdl meta.block.architecture.body.vhdl meta.block.process.body.vhdl meta.block.if.conditional.vhdl meta.group.parens.vhdl punctuation.group.parens.begin.vhdl ``` The parenthesis in a `case` expression is scoped as...