Readon
Readon
> One quick note: I'm not sure that we should go down the route to basically drop verilog support (which we'd kind of do if we have temporal sequences in...
> ah well that's an interesting discussion, I was thinking about it this this afternoon, and while someone better versed in formal verification might proove this wrong, I had a...
> > > One quick note: I'm not sure that we should go down the route to basically drop verilog support (which we'd kind of do if we have temporal...
> When the `spinal.core.formal.GlobalClock()` is used, an invalid name is given to the signal in VHDL. Which generates with VHDL to: > > ```vhdl > signal _global_clk : std_logic; >...
> > if I understand right, after _global_clk is changed to global_clk it would work? > > Yes > > > However, how would it be to sperate the global...
> onetheless, maybe we should add a Phase that checks the naming for VHDL signals and print an error. Generating invalid VHDL is not good even if it is by...
There is a shouldFail function which pass while verification failed. You can add the vhdl verification cases in the same file as verilog do.
your dut have not driven by clock. it's just combinational
Maybe you could include the tester of yours, then. Or just pick up some existing formal verification checker like FormalMuxTester/FormalDemuxTester as an testcase first. Keep the consistency with the existing...
What is missing while CI? Does it require ghdl 4.1? Planning on upgrade the docker image for CI.