Robert Schilling
Robert Schilling
@matutem I now removed all external bypass ports to the AST and to the lifecycle controller. For LC, the bypass is routed to its ack signal on the top-level to...
This is now finally CI green. @matutem Could you take another look?
> For next time, it might be nice to split the PR into smaller pieces (and maybe open several chained PRs if there are dependencies). It might be a bit...
I updated the PR and added a new ipgen parameter that allows enabling or disabling the external clock bypasses as requested. Further the signal indicating a calibrated clock was added...
Thanks @rswarbrick for looking into this. I added your suggestions into the templating.
> or anyone looking at this, it's a bit tricky to figure out why the SW build failed. If I have read things right, the error message is: SW build...
I think in DV we can get away with only unquifying the core files, the tb.sv (for the module instantiation) and the bind target (which uses the DUT name) as...
@martin-velay I reworkd the templates. The only independent file where no templating is needed is `ac_range_check_dut_cfg.sv`. I left that for now. All others have templating requirements.
> Hi @Razer6! Is this PR still relevant? (Is there anything to extract or should it just be closed?) Yes it is. I am just about rebeasing. @davidschrammel is making...
@rswarbrick @martin-velay Can you please take a look? I properly templified the DV code now to deal with different module name instances. Code is tested downstream with different instances.