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RTimothyEdwards
Netgen complete LVS tool for comparing SPICE or verilog netlists
Tested on 2 cases that had problems before the fix. Have not tested with LEF based LVS. Fixes #66
Some designs have module names up to 152 characters in length which causes netgen to terminate abnormally.
When cells with different names are equated, the equivalence of cells with the same name is broken. This change allows the equivalence of same named cells to be reestablished after...
netgen 1.5.233 The layout contains prefixed and unprefixed cells that should match to the same unprefixed name in gl verilog. eg. `BO_sky130_fd_sc_hd__clkbuf_8` and `sky130_fd_sc_hd__clkbuf_8` should both match `sky130_fd_sc_hd__clkbuf_8` in the...
I can't think of a use case where we'd want black boxes to be flattened out of existence. However, in the pre-compare name check, if a black box doesn't exist...
Since merging code related to pull request #59, netgen no longer correctly handles implicit pins in verilog. This issue is caused by the fact that verilog syntax allows pins to...
This removes the proxy pin code and forces pin matching. Any pin mismatches (even if disconnected) cause cell flattening. There may be some additional cosmetic changes. Highly recommend **NOT** merging...
Specifying cells with the `-noflatten` option should prevent those cells from being flattened. However, if there is a difference in the cell counts, netgen will flatten cells regardless of whether...
In the attached test case, the design has two ports with the same name but one is uppercase and the other is lower case. Netgen reports one pin mismatch because...
When I run `make install`, I get this error: ```bash --- installing executable to /usr/local/bin --- installing run-time files to /usr/local/lib make[2]: *** No rule to make target '/usr/local/lib/netgen/python', needed...
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Netgen complete LVS tool for comparing SPICE or verilog netlists