Space-Invaders
Space-Invaders copied to clipboard
Space Invaders in Verilog for the iCE40 H1K
- Space-Invaders
Port of VHDL Space Invaders (https://github.com/David-Estevez/spaceinvaders) to Verilog for the iCE40 H1K
- Video
https://www.youtube.com/watch?v=zD_Xy7i3Ies
TODO
- Tone generator
- Two players
- Different Levels
- Keeping score of how many invaders you have destroyed
- Read the sprite info from a plain text file. Research how to make 32x32 pixel map from picture
- Create extensive testbenches for all modules
- Use SystemVerilog asserts to verify model
- Trunk modules should only have instantiations of other modules. Leaf modules should implement the logic
- Use Mealy FSM for sequential logic (All modules but sprite_drawer). More specifically, use two process design method (Gaisler)
- Use homogenous naming and coding convention
- How to sinthesize & simulate :PROPERTIES: :CUSTOM_ID: how-to-sinthesize-simulate :END:
** Top Module :PROPERTIES: :CUSTOM_ID: top-module :END:
- Simulate top module
#+BEGIN_EXAMPLE $ make sim #+END_EXAMPLE
- Sinthesize top module:
#+BEGIN_EXAMPLE $ make bin #+END_EXAMPLE
- Upload to FPGA
#+BEGIN_EXAMPLE $ make upload #+END_EXAMPLE
** Submodules :PROPERTIES: :CUSTOM_ID: submodules :END:
- Simulate sub-module
Given a submodule called =file.v=, and a corresponding testbench called =file_tb.v=, you can simulate the sub-module using:
#+BEGIN_EXAMPLE $ make MODULE=module sim #+END_EXAMPLE
- Formal verification status All assertions are SVA (SystemVerilog assertions). | Module | inmediate assertions | concurrent assertions | |-------------------------+----------------------+-----------------------| | ship | done | done | | gameplay | done | done | | invaders | done | done | | bullet | done | done | | timer_1us | done | done | | player | n/a | n/a | | edge_detector_debouncer | pending | pending | | vga_controller | pending | pending | | sprite_drawer | pending | pending |
** Instructions for using the evaluation version of TabbyCAD #+begin_src shell :shebang #!/bin/bash -i :results output export YOSYSHQ_LICENSE=/home/roland/tabbycad-eval-RolandCoeurjolyLechuga-240115.lic cd ~/Space-Invaders ~/tabby/bin/sby -f formal/ship.sby #+end_src
- Known issues ** Unexpected response from solver: bash: warning: setlocale: LC_ALL: cannot change locale (en_US.UTF-8)