isWireArray(termtype) is missing in /utils/signaltype.py

[teaalltr]

Generating LALR tables
WARNING: 183 shift/reduce conflicts
Traceback (most recent call last):
  File "examples/example_dataflow_codegen.py", line 95, in <module>
    main()
  File "examples/example_dataflow_codegen.py", line 87, in main
    code = codegen.generateCode(options.searchtarget)
  File "/mnt/c/Users/savo9/OneDrive/Desktop/pyverilog/pyverilog/dataflow/dataflow_codegen.py", line 113, in generateCode
    return self.generateEntireCode()
  File "/mnt/c/Users/savo9/OneDrive/Desktop/pyverilog/pyverilog/dataflow/dataflow_codegen.py", line 120, in generateEntireCode
    terms, parameter, assign, always_clockedge, always_combination = self.getEntire()
  File "/mnt/c/Users/savo9/OneDrive/Desktop/pyverilog/pyverilog/dataflow/subset.py", line 80, in getEntire
    return self._discretion(visited_binddict, visited_sources)
  File "/mnt/c/Users/savo9/OneDrive/Desktop/pyverilog/pyverilog/dataflow/subset.py", line 104, in _discretion
    assign_type = self.getAssignType(left, right)
  File "/mnt/c/Users/savo9/OneDrive/Desktop/pyverilog/pyverilog/dataflow/merge.py", line 72, in getAssignType
    if signaltype.isWireArray(termtype):
AttributeError: module 'pyverilog.utils.signaltype' has no attribute 'isWireArray'

[roy-pstr]

Same here.